xref: /linux/Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.yaml (revision 7f71507851fc7764b36a3221839607d3a45c2025) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/interrupt-controller/fsl,mu-msi.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Freescale/NXP i.MX Messaging Unit (MU) work as msi controller
8
9maintainers:
10  - Frank Li <Frank.Li@nxp.com>
11
12description: |
13  The Messaging Unit module enables two processors within the SoC to
14  communicate and coordinate by passing messages (e.g. data, status
15  and control) through the MU interface. The MU also provides the ability
16  for one processor (A side) to signal the other processor (B side) using
17  interrupts.
18
19  Because the MU manages the messaging between processors, the MU uses
20  different clocks (from each side of the different peripheral buses).
21  Therefore, the MU must synchronize the accesses from one side to the
22  other. The MU accomplishes synchronization using two sets of matching
23  registers (Processor A-side, Processor B-side).
24
25  MU can work as msi interrupt controller to do doorbell
26
27allOf:
28  - $ref: /schemas/interrupt-controller/msi-controller.yaml#
29
30properties:
31  compatible:
32    enum:
33      - fsl,imx6sx-mu-msi
34      - fsl,imx7ulp-mu-msi
35      - fsl,imx8ulp-mu-msi
36      - fsl,imx8ulp-mu-msi-s4
37
38  reg:
39    items:
40      - description: a side register base address
41      - description: b side register base address
42
43  reg-names:
44    items:
45      - const: processor-a-side
46      - const: processor-b-side
47
48  interrupts:
49    description: a side interrupt number.
50    maxItems: 1
51
52  clocks:
53    maxItems: 1
54
55  power-domains:
56    items:
57      - description: a side power domain
58      - description: b side power domain
59
60  power-domain-names:
61    items:
62      - const: processor-a-side
63      - const: processor-b-side
64
65  msi-controller: true
66
67  "#msi-cells":
68    const: 0
69
70required:
71  - compatible
72  - reg
73  - interrupts
74  - msi-controller
75  - "#msi-cells"
76
77additionalProperties: false
78
79examples:
80  - |
81    #include <dt-bindings/interrupt-controller/arm-gic.h>
82    #include <dt-bindings/firmware/imx/rsrc.h>
83
84    msi-controller@5d270000 {
85        compatible = "fsl,imx6sx-mu-msi";
86        msi-controller;
87        #msi-cells = <0>;
88        reg = <0x5d270000 0x10000>,     /* A side */
89              <0x5d300000 0x10000>;     /* B side */
90        reg-names = "processor-a-side", "processor-b-side";
91        interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
92        power-domains = <&pd IMX_SC_R_MU_12A>,
93                        <&pd IMX_SC_R_MU_12B>;
94        power-domain-names = "processor-a-side", "processor-b-side";
95    };
96