xref: /linux/Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml (revision c0f182c979cfead8fff08108a11fbd2fe885dd33)
1*9773c540SCaleb James DeLisle# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*9773c540SCaleb James DeLisle%YAML 1.2
3*9773c540SCaleb James DeLisle---
4*9773c540SCaleb James DeLisle$id: http://devicetree.org/schemas/interrupt-controller/econet,en751221-intc.yaml#
5*9773c540SCaleb James DeLisle$schema: http://devicetree.org/meta-schemas/core.yaml#
6*9773c540SCaleb James DeLisle
7*9773c540SCaleb James DeLisletitle: EcoNet EN751221 Interrupt Controller
8*9773c540SCaleb James DeLisle
9*9773c540SCaleb James DeLislemaintainers:
10*9773c540SCaleb James DeLisle  - Caleb James DeLisle <cjd@cjdns.fr>
11*9773c540SCaleb James DeLisle
12*9773c540SCaleb James DeLisledescription:
13*9773c540SCaleb James DeLisle  The EcoNet EN751221 Interrupt Controller is a simple interrupt controller
14*9773c540SCaleb James DeLisle  designed for the MIPS 34Kc MT SMP processor with 2 VPEs. Each interrupt can
15*9773c540SCaleb James DeLisle  be routed to either VPE but not both, so to support per-CPU interrupts, a
16*9773c540SCaleb James DeLisle  secondary IRQ number is allocated to control masking/unmasking on VPE#1. For
17*9773c540SCaleb James DeLisle  lack of a better term we call these "shadow interrupts". The assignment of
18*9773c540SCaleb James DeLisle  shadow interrupts is defined by the SoC integrator when wiring the interrupt
19*9773c540SCaleb James DeLisle  lines, so they are configurable in the device tree.
20*9773c540SCaleb James DeLisle
21*9773c540SCaleb James DeLisleallOf:
22*9773c540SCaleb James DeLisle  - $ref: /schemas/interrupt-controller.yaml#
23*9773c540SCaleb James DeLisle
24*9773c540SCaleb James DeLisleproperties:
25*9773c540SCaleb James DeLisle  compatible:
26*9773c540SCaleb James DeLisle    const: econet,en751221-intc
27*9773c540SCaleb James DeLisle
28*9773c540SCaleb James DeLisle  reg:
29*9773c540SCaleb James DeLisle    maxItems: 1
30*9773c540SCaleb James DeLisle
31*9773c540SCaleb James DeLisle  "#interrupt-cells":
32*9773c540SCaleb James DeLisle    const: 1
33*9773c540SCaleb James DeLisle
34*9773c540SCaleb James DeLisle  interrupt-controller: true
35*9773c540SCaleb James DeLisle
36*9773c540SCaleb James DeLisle  interrupts:
37*9773c540SCaleb James DeLisle    maxItems: 1
38*9773c540SCaleb James DeLisle    description: Interrupt line connecting this controller to its parent.
39*9773c540SCaleb James DeLisle
40*9773c540SCaleb James DeLisle  econet,shadow-interrupts:
41*9773c540SCaleb James DeLisle    $ref: /schemas/types.yaml#/definitions/uint32-matrix
42*9773c540SCaleb James DeLisle    description:
43*9773c540SCaleb James DeLisle      An array of interrupt number pairs where each pair represents a shadow
44*9773c540SCaleb James DeLisle      interrupt relationship. The first number in each pair is the primary IRQ,
45*9773c540SCaleb James DeLisle      and the second is its shadow IRQ used for VPE#1 control. For example,
46*9773c540SCaleb James DeLisle      <8 3> means IRQ 8 is shadowed by IRQ 3, so IRQ 3 cannot be mapped, but
47*9773c540SCaleb James DeLisle      when VPE#1 requests IRQ 8, it will manipulate the IRQ 3 mask bit.
48*9773c540SCaleb James DeLisle    minItems: 1
49*9773c540SCaleb James DeLisle    maxItems: 20
50*9773c540SCaleb James DeLisle    items:
51*9773c540SCaleb James DeLisle      items:
52*9773c540SCaleb James DeLisle        - description: primary per-CPU IRQ
53*9773c540SCaleb James DeLisle        - description: shadow IRQ number
54*9773c540SCaleb James DeLisle
55*9773c540SCaleb James DeLislerequired:
56*9773c540SCaleb James DeLisle  - compatible
57*9773c540SCaleb James DeLisle  - reg
58*9773c540SCaleb James DeLisle  - interrupt-controller
59*9773c540SCaleb James DeLisle  - "#interrupt-cells"
60*9773c540SCaleb James DeLisle  - interrupts
61*9773c540SCaleb James DeLisle
62*9773c540SCaleb James DeLisleadditionalProperties: false
63*9773c540SCaleb James DeLisle
64*9773c540SCaleb James DeLisleexamples:
65*9773c540SCaleb James DeLisle  - |
66*9773c540SCaleb James DeLisle    interrupt-controller@1fb40000 {
67*9773c540SCaleb James DeLisle        compatible = "econet,en751221-intc";
68*9773c540SCaleb James DeLisle        reg = <0x1fb40000 0x100>;
69*9773c540SCaleb James DeLisle
70*9773c540SCaleb James DeLisle        interrupt-controller;
71*9773c540SCaleb James DeLisle        #interrupt-cells = <1>;
72*9773c540SCaleb James DeLisle
73*9773c540SCaleb James DeLisle        interrupt-parent = <&cpuintc>;
74*9773c540SCaleb James DeLisle        interrupts = <2>;
75*9773c540SCaleb James DeLisle
76*9773c540SCaleb James DeLisle        econet,shadow-interrupts = <7 2>, <8 3>, <13 12>, <30 29>;
77*9773c540SCaleb James DeLisle    };
78*9773c540SCaleb James DeLisle...
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