1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/interrupt-controller/chrp,open-pic.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Open PIC Interrupt Controller 8 9maintainers: 10 - Rob Herring <robh@kernel.org> 11 12description: 13 This binding specifies what properties must be available in the device tree 14 representation of an Open PIC compliant interrupt controller. This binding is 15 based on the binding defined for Open PIC in [1] and is a superset of that 16 binding. 17 18properties: 19 compatible: 20 oneOf: 21 - items: 22 - const: fsl,mpic 23 - const: chrp,open-pic 24 - const: chrp,open-pic 25 26 device_type: 27 const: open-pci 28 deprecated: true 29 30 reg: 31 maxItems: 1 32 33 interrupt-controller: true 34 35 '#address-cells': 36 const: 0 37 38 '#interrupt-cells': 39 description: 40 A value of 4 means that interrupt specifiers contain the interrupt-type or 41 type-specific information cells. 42 enum: [ 2, 4 ] 43 44 pic-no-reset: 45 description: Indicates the PIC shall not be reset during runtime initialization. 46 type: boolean 47 48 single-cpu-affinity: 49 description: 50 If present, non-IPI interrupts will be routed to a single CPU at a time. 51 type: boolean 52 53 last-interrupt-source: 54 description: 55 Some MPICs do not correctly report the number of hardware sources in the 56 global feature registers. This value, if specified, overrides the value 57 read from MPIC_GREG_FEATURE_LAST_SRC. 58 $ref: /schemas/types.yaml#/definitions/uint32 59 60required: 61 - compatible 62 - reg 63 - interrupt-controller 64 - '#address-cells' 65 - '#interrupt-cells' 66 67additionalProperties: false 68 69examples: 70 - | 71 interrupt-controller@40000 { 72 compatible = "chrp,open-pic"; 73 reg = <0x40000 0x40000>; 74 interrupt-controller; 75 #address-cells = <0>; 76 #interrupt-cells = <2>; 77 pic-no-reset; 78 }; 79