1*928504c5SRob Herring (Arm)# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*928504c5SRob Herring (Arm)%YAML 1.2 3*928504c5SRob Herring (Arm)--- 4*928504c5SRob Herring (Arm)$id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm6345-l1-intc.yaml# 5*928504c5SRob Herring (Arm)$schema: http://devicetree.org/meta-schemas/core.yaml# 6*928504c5SRob Herring (Arm) 7*928504c5SRob Herring (Arm)title: Broadcom BCM6345-style Level 1 interrupt controller 8*928504c5SRob Herring (Arm) 9*928504c5SRob Herring (Arm)maintainers: 10*928504c5SRob Herring (Arm) - Simon Arlott <simon@octiron.net> 11*928504c5SRob Herring (Arm) 12*928504c5SRob Herring (Arm)description: > 13*928504c5SRob Herring (Arm) This block is a first level interrupt controller that is typically connected 14*928504c5SRob Herring (Arm) directly to one of the HW INT lines on each CPU. 15*928504c5SRob Herring (Arm) 16*928504c5SRob Herring (Arm) Key elements of the hardware design include: 17*928504c5SRob Herring (Arm) 18*928504c5SRob Herring (Arm) - 32, 64 or 128 incoming level IRQ lines 19*928504c5SRob Herring (Arm) 20*928504c5SRob Herring (Arm) - Most onchip peripherals are wired directly to an L1 input 21*928504c5SRob Herring (Arm) 22*928504c5SRob Herring (Arm) - A separate instance of the register set for each CPU, allowing individual 23*928504c5SRob Herring (Arm) peripheral IRQs to be routed to any CPU 24*928504c5SRob Herring (Arm) 25*928504c5SRob Herring (Arm) - Contains one or more enable/status word pairs per CPU 26*928504c5SRob Herring (Arm) 27*928504c5SRob Herring (Arm) - No atomic set/clear operations 28*928504c5SRob Herring (Arm) 29*928504c5SRob Herring (Arm) - No polarity/level/edge settings 30*928504c5SRob Herring (Arm) 31*928504c5SRob Herring (Arm) - No FIFO or priority encoder logic; software is expected to read all 32*928504c5SRob Herring (Arm) 2-4 status words to determine which IRQs are pending 33*928504c5SRob Herring (Arm) 34*928504c5SRob Herring (Arm) If multiple reg ranges and interrupt-parent entries are present on an SMP 35*928504c5SRob Herring (Arm) system, the driver will allow IRQ SMP affinity to be set up through the 36*928504c5SRob Herring (Arm) /proc/irq/ interface. In the simplest possible configuration, only one 37*928504c5SRob Herring (Arm) reg range and one interrupt-parent is needed. 38*928504c5SRob Herring (Arm) 39*928504c5SRob Herring (Arm) The driver operates in native CPU endian by default, there is no support for 40*928504c5SRob Herring (Arm) specifying an alternative endianness. 41*928504c5SRob Herring (Arm) 42*928504c5SRob Herring (Arm)properties: 43*928504c5SRob Herring (Arm) compatible: 44*928504c5SRob Herring (Arm) const: brcm,bcm6345-l1-intc 45*928504c5SRob Herring (Arm) 46*928504c5SRob Herring (Arm) reg: 47*928504c5SRob Herring (Arm) description: One entry per CPU core 48*928504c5SRob Herring (Arm) minItems: 1 49*928504c5SRob Herring (Arm) maxItems: 2 50*928504c5SRob Herring (Arm) 51*928504c5SRob Herring (Arm) interrupt-controller: true 52*928504c5SRob Herring (Arm) 53*928504c5SRob Herring (Arm) "#interrupt-cells": 54*928504c5SRob Herring (Arm) const: 1 55*928504c5SRob Herring (Arm) 56*928504c5SRob Herring (Arm) interrupts: 57*928504c5SRob Herring (Arm) description: One entry per CPU core 58*928504c5SRob Herring (Arm) minItems: 1 59*928504c5SRob Herring (Arm) maxItems: 2 60*928504c5SRob Herring (Arm) 61*928504c5SRob Herring (Arm)required: 62*928504c5SRob Herring (Arm) - compatible 63*928504c5SRob Herring (Arm) - reg 64*928504c5SRob Herring (Arm) - interrupt-controller 65*928504c5SRob Herring (Arm) - '#interrupt-cells' 66*928504c5SRob Herring (Arm) - interrupts 67*928504c5SRob Herring (Arm) 68*928504c5SRob Herring (Arm)additionalProperties: false 69*928504c5SRob Herring (Arm) 70*928504c5SRob Herring (Arm)examples: 71*928504c5SRob Herring (Arm) - | 72*928504c5SRob Herring (Arm) interrupt-controller@10000000 { 73*928504c5SRob Herring (Arm) compatible = "brcm,bcm6345-l1-intc"; 74*928504c5SRob Herring (Arm) reg = <0x10000020 0x20>, 75*928504c5SRob Herring (Arm) <0x10000040 0x20>; 76*928504c5SRob Herring (Arm) 77*928504c5SRob Herring (Arm) interrupt-controller; 78*928504c5SRob Herring (Arm) #interrupt-cells = <1>; 79*928504c5SRob Herring (Arm) 80*928504c5SRob Herring (Arm) interrupts = <2>, <3>; 81*928504c5SRob Herring (Arm) }; 82