1BCM2835 Top-Level ("ARMCTRL") Interrupt Controller 2 3The BCM2835 contains a custom top-level interrupt controller, which supports 472 interrupt sources using a 2-level register scheme. The interrupt 5controller, or the HW block containing it, is referred to occasionally 6as "armctrl" in the SoC documentation, hence naming of this binding. 7 8The BCM2836 contains the same interrupt controller with the same 9interrupts, but the per-CPU interrupt controller is the root, and an 10interrupt there indicates that the ARMCTRL has an interrupt to handle. 11 12Required properties: 13 14- compatible : should be "brcm,bcm2835-armctrl-ic" or 15 "brcm,bcm2836-armctrl-ic" 16- reg : Specifies base physical address and size of the registers. 17- interrupt-controller : Identifies the node as an interrupt controller 18- #interrupt-cells : Specifies the number of cells needed to encode an 19 interrupt source. The value shall be 2. 20 21 The 1st cell is the interrupt bank; 0 for interrupts in the "IRQ basic 22 pending" register, or 1/2 respectively for interrupts in the "IRQ pending 23 1/2" register. 24 25 The 2nd cell contains the interrupt number within the bank. Valid values 26 are 0..7 for bank 0, and 0..31 for bank 1. 27 28Additional required properties for brcm,bcm2836-armctrl-ic: 29- interrupts : Specifies the interrupt on the parent for this interrupt 30 controller to handle. 31 32The interrupt sources are as follows: 33 34Bank 0: 350: ARM_TIMER 361: ARM_MAILBOX 372: ARM_DOORBELL_0 383: ARM_DOORBELL_1 394: VPU0_HALTED 405: VPU1_HALTED 416: ILLEGAL_TYPE0 427: ILLEGAL_TYPE1 43 44Bank 1: 450: TIMER0 461: TIMER1 472: TIMER2 483: TIMER3 494: CODEC0 505: CODEC1 516: CODEC2 527: VC_JPEG 538: ISP 549: VC_USB 5510: VC_3D 5611: TRANSPOSER 5712: MULTICORESYNC0 5813: MULTICORESYNC1 5914: MULTICORESYNC2 6015: MULTICORESYNC3 6116: DMA0 6217: DMA1 6318: VC_DMA2 6419: VC_DMA3 6520: DMA4 6621: DMA5 6722: DMA6 6823: DMA7 6924: DMA8 7025: DMA9 7126: DMA10 7227: DMA11-14 - shared interrupt for DMA 11 to 14 7328: DMAALL - triggers on all dma interrupts (including channel 15) 7429: AUX 7530: ARM 7631: VPUDMA 77 78Bank 2: 790: HOSTPORT 801: VIDEOSCALER 812: CCP2TX 823: SDC 834: DSI0 845: AVE 856: CAM0 867: CAM1 878: HDMI0 889: HDMI1 8910: PIXELVALVE1 9011: I2CSPISLV 9112: DSI1 9213: PWA0 9314: PWA1 9415: CPR 9516: SMI 9617: GPIO0 9718: GPIO1 9819: GPIO2 9920: GPIO3 10021: VC_I2C 10122: VC_SPI 10223: VC_I2SPCM 10324: VC_SDIO 10425: VC_UART 10526: SLIMBUS 10627: VEC 10728: CPG 10829: RNG 10930: VC_ARASANSDIO 11031: AVSPMON 111 112Example: 113 114/* BCM2835, first level */ 115intc: interrupt-controller { 116 compatible = "brcm,bcm2835-armctrl-ic"; 117 reg = <0x7e00b200 0x200>; 118 interrupt-controller; 119 #interrupt-cells = <2>; 120}; 121 122/* BCM2836, second level */ 123intc: interrupt-controller { 124 compatible = "brcm,bcm2836-armctrl-ic"; 125 reg = <0x7e00b200 0x200>; 126 interrupt-controller; 127 #interrupt-cells = <2>; 128 129 interrupt-parent = <&local_intc>; 130 interrupts = <8>; 131}; 132