xref: /linux/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml (revision de80193308f43d3ae52cd3561e8ba77cd1437311) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7120-l2-intc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Broadcom BCM7120-style Level 2 and Broadcom BCM3380 Level 1 / Level 2
8
9maintainers:
10  - Florian Fainelli <f.fainelli@gmail.com>
11
12description: >
13  This interrupt controller hardware is a second level interrupt controller that
14  is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
15  platforms. It can be found on BCM7xxx products starting with BCM7120.
16
17  Such an interrupt controller has the following hardware design:
18
19  - outputs multiple interrupts signals towards its interrupt controller parent
20
21  - controls how some of the interrupts will be flowing, whether they will
22    directly output an interrupt signal towards the interrupt controller parent,
23    or if they will output an interrupt signal at this 2nd level interrupt
24    controller, in particular for UARTs
25
26  - has one 32-bit enable word and one 32-bit status word
27
28  - no atomic set/clear operations
29
30  - not all bits within the interrupt controller actually map to an interrupt
31
32  The typical hardware layout for this controller is represented below:
33
34  2nd level interrupt line		Outputs for the parent controller (e.g: ARM GIC)
35
36  0 -----[ MUX ] ------------|==========> GIC interrupt 75
37            \-----------\
38                         |
39  1 -----[ MUX ] --------)---|==========> GIC interrupt 76
40            \------------|
41                         |
42  2 -----[ MUX ] --------)---|==========> GIC interrupt 77
43            \------------|
44                         |
45  3 ---------------------|
46  4 ---------------------|
47  5 ---------------------|
48  7 ---------------------|---|===========> GIC interrupt 66
49  9 ---------------------|
50  10 --------------------|
51  11 --------------------/
52
53  6 ------------------------\
54                            |===========> GIC interrupt 64
55  8 ------------------------/
56
57  12 ........................ X
58  13 ........................ X           (not connected)
59  ..
60  31 ........................ X
61
62  The BCM3380 Level 1 / Level 2 interrupt controller shows up in various forms
63  on many BCM338x/BCM63xx chipsets. It has the following properties:
64
65  - outputs a single interrupt signal to its interrupt controller parent
66
67  - contains one or more enable/status word pairs, which often appear at
68    different offsets in different blocks
69
70  - no atomic set/clear operations
71
72allOf:
73  - $ref: /schemas/interrupt-controller.yaml#
74
75properties:
76  compatible:
77    items:
78      - enum:
79          - brcm,bcm7120-l2-intc
80          - brcm,bcm3380-l2-intc
81
82  reg:
83    minItems: 1
84    maxItems: 4
85    description: >
86      Specifies the base physical address and size of the registers
87
88  interrupt-controller: true
89
90  "#interrupt-cells":
91    const: 1
92
93  interrupts:
94    minItems: 1
95    maxItems: 32
96
97  brcm,int-map-mask:
98    $ref: /schemas/types.yaml#/definitions/uint32-array
99    description: >
100      32-bits bit mask describing how many and which interrupts are wired to
101      this 2nd level interrupt controller, and how they match their respective
102      interrupt parents. Should match exactly the number of interrupts
103      specified in the 'interrupts' property.
104
105  brcm,irq-can-wake:
106    type: boolean
107    description: >
108      If present, this means the L2 controller can be used as a wakeup source
109      for system suspend/resume.
110
111  brcm,int-fwd-mask:
112    $ref: /schemas/types.yaml#/definitions/uint32-array
113    maxItems: 1
114    description: >
115      if present, a bit mask to configure the interrupts which have a mux gate,
116      typically UARTs. Setting these bits will make their respective interrupt
117      outputs bypass this 2nd level interrupt controller completely; it is
118      completely transparent for the interrupt controller parent. This should
119      have one 32-bit word per enable/status pair.
120
121additionalProperties: false
122
123required:
124  - compatible
125  - reg
126  - interrupt-controller
127  - "#interrupt-cells"
128  - interrupts
129
130examples:
131  - |
132    irq0_intc: interrupt-controller@f0406800 {
133      compatible = "brcm,bcm7120-l2-intc";
134      interrupt-parent = <&intc>;
135      #interrupt-cells = <1>;
136      reg = <0xf0406800 0x8>;
137      interrupt-controller;
138      interrupts = <0x0 0x42 0x0>, <0x0 0x40 0x0>;
139      brcm,int-map-mask = <0xeb8>, <0x140>;
140      brcm,int-fwd-mask = <0x7>;
141    };
142
143  - |
144    irq1_intc: interrupt-controller@10000020 {
145       compatible = "brcm,bcm3380-l2-intc";
146       reg = <0x10000024 0x4>, <0x1000002c 0x4>,
147             <0x10000020 0x4>, <0x10000028 0x4>;
148       interrupt-controller;
149       #interrupt-cells = <1>;
150       interrupt-parent = <&cpu_intc>;
151       interrupts = <2>;
152    };
153