1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-interrupt.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: ASPEED AST2700 Interrupt Controllers (INTC0/INTC1) 8 9description: | 10 The ASPEED AST2700 SoC integrates two interrupt controller designs: 11 12 - INTC0: Primary controller that routes interrupt sources to upstream, 13 processor-specific interrupt controllers 14 15 - INTC1: Secondary controller whose interrupt outputs feed into INTC0 16 17 The SoC contains four processors to which interrupts can be routed: 18 19 - PSP: Primary Service Processor (Cortex-A35) 20 - SSP: Secondary Service Processor (Cortex-M4) 21 - TSP: Tertiary Service Processor (Cortex-M4) 22 - BMCU: Boot MCU (a RISC-V microcontroller) 23 24 The following diagram illustrates the overall architecture of the 25 ASPEED AST2700 interrupt controllers: 26 27 +-----------+ +-----------+ 28 | INTC0 | | INTC1(0) | 29 +-----------+ +-----------+ 30 | Router | +-----------+ | Router | 31 | out int | +Peripheral + | out int | 32 +-----------+ | 0 0 <-+Controllers+ | INTM | +-----------+ 33 |PSP GIC <-|---+ . . | +-----------+ | . . <-+Peripheral + 34 +-----------+ | . . | | . . | +Controllers+ 35 +-----------+ | . . | | . . | +-----------+ 36 |SSP NVIC <-|---+ . . <----------------+ . . | 37 +-----------+ | . . | | . . | 38 +-----------+ | . . <-------- | . . | 39 |TSP NVIC <-|---+ . . | | ----+ . . | 40 +-----------+ | . . | | | | O P | 41 | . . | | | +-----------+ 42 | . . <---- | -------------------- 43 | . . | | | +-----------+ | 44 | M N | | ---------+ INTC1(1) | | 45 +-----------+ | +-----------+ | 46 | . | 47 | +-----------+ | 48 -------------+ INTC1(N) | | 49 +-----------+ | 50 +--------------+ | 51 + BMCU APLIC <-+--------------------------------------------- 52 +--------------+ 53 54 INTC0 supports: 55 - 128 local peripheral interrupt inputs 56 - Fan-in from up to three INTC1 instances via banked interrupt lines (INTM) 57 - Local peripheral interrupt outputs 58 - Merged interrupt outputs 59 - Software interrupt outputs (SWINT) 60 - Configurable interrupt routes targeting the PSP, SSP, and TSP 61 62 INTC1 supports: 63 - 192 local peripheral interrupt inputs 64 - Banked interrupt outputs (INTM, 5 x 6 banks x 32 interrupts per bank) 65 - Configurable interrupt routes targeting the PSP, SSP, TSP, and BMCU 66 67 One INTC1 instance is always present, on the SoC's IO die. A further two 68 instances may be attached to the SoC's one INTC0 instance via LTPI (LVDS 69 Tunneling Protocol & Interface). 70 71 Interrupt numbering model 72 ------------------------- 73 The binding uses a controller-local numbering model. Peripheral device 74 nodes use the INTCx local interrupt number (hwirq) in their 'interrupts' or 75 'interrupts-extended' properties. 76 77 For AST2700, INTC0 exposes the following (inclusive) input ranges: 78 79 - 000..479: Independent interrupts 80 - 480..489: INTM0-INTM9 81 - 490..499: INTM10-INTM19 82 - 500..509: INTM20-INTM29 83 - 510..519: INTM30-INTM39 84 - 520..529: INTM40-INTM49 85 86 INTC0's (inclusive) output ranges are as follows: 87 88 - 000..127: 1:1 local peripheral interrupt output to PSP 89 - 144..151: Software interrupts from the SSP output to PSP 90 - 152..159: Software interrupts from the TSP output to PSP 91 - 192..201: INTM0-INTM9 banked outputs to PSP 92 - 208..217: INTM30-INTM39 banked outputs to PSP 93 - 224..233: INTM40-INTM49 banked outputs to PSP 94 - 256..383: 1:1 local peripheral interrupt output to SSP 95 - 384..393: INTM10-INTM19 banked outputs to SSP 96 - 400..407: Software interrupts from the PSP output to SSP 97 - 408..415: Software interrupts from the TSP output to SSP 98 - 426..553: 1:1 local peripheral interrupt output to TSP 99 - 554..563: INTM20-INTM29 banked outputs to TSP 100 - 570..577: Software interrupts from the PSP output to TSP 101 - 578..585: Software interrupts from the SSP output to TSP 102 103 Inputs and outputs for INTC1 instances are context-dependent. However, for the 104 first instance of INTC1, the (inclusive) output ranges are: 105 106 - 00..05: INTM0-INTM5 107 - 10..15: INTM10-INTM15 108 - 20..25: INTM20-INTM25 109 - 30..35: INTM30-INTM35 110 - 40..45: INTM40-INTM45 111 - 50..50: BootMCU 112 113maintainers: 114 - Ryan Chen <ryan_chen@aspeedtech.com> 115 - Andrew Jeffery <andrew@codeconstruct.com.au> 116 117properties: 118 compatible: 119 enum: 120 - aspeed,ast2700-intc0 121 - aspeed,ast2700-intc1 122 123 reg: 124 maxItems: 1 125 126 interrupt-controller: true 127 128 '#interrupt-cells': 129 const: 1 130 description: Single cell encoding the INTC local interrupt number (hwirq). 131 132 aspeed,interrupt-ranges: 133 description: | 134 Describes how ranges of controller output pins are routed to a parent 135 interrupt controller. 136 137 Each range entry is encoded as: 138 139 <out count phandle parent-specifier...> 140 141 where: 142 - out: First controller interrupt output index in the range. 143 - count: Number of consecutive controller interrupt outputs and parent 144 interrupt inputs in this range. 145 - phandle: Phandle to the parent interrupt controller node. 146 - parent-specifier: Interrupt specifier, as defined by the parent 147 interrupt controller binding. 148 $ref: /schemas/types.yaml#/definitions/uint32-array 149 minItems: 3 150 items: 151 description: Range descriptors with a parent interrupt specifier. 152 153required: 154 - compatible 155 - reg 156 - interrupt-controller 157 - '#interrupt-cells' 158 - aspeed,interrupt-ranges 159 160additionalProperties: false 161 162examples: 163 - | 164 #include <dt-bindings/interrupt-controller/arm-gic.h> 165 166 interrupt-controller@12100000 { 167 compatible = "aspeed,ast2700-intc0"; 168 reg = <0x12100000 0x3b00>; 169 interrupt-parent = <&gic>; 170 interrupt-controller; 171 #interrupt-cells = <1>; 172 173 aspeed,interrupt-ranges = 174 <0 128 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 175 <144 8 &gic GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 176 <152 8 &gic GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 177 <192 10 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 178 <208 10 &gic GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 179 <224 10 &gic GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 180 <256 128 &ssp_nvic 0 0>, 181 <384 10 &ssp_nvic 160 0>, 182 <400 8 &ssp_nvic 144 0>, 183 <408 8 &ssp_nvic 152 0>, 184 <426 128 &tsp_nvic 0 0>, 185 <554 10 &tsp_nvic 160 0>, 186 <570 8 &tsp_nvic 144 0>, 187 <578 8 &tsp_nvic 152 0>; 188 }; 189