xref: /linux/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml (revision d30c1683aaecb93d2ab95685dc4300a33d3cea7a) 
1# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-intc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Aspeed AST2700 Interrupt Controller
8
9description:
10  This interrupt controller hardware is second level interrupt controller that
11  is hooked to a parent interrupt controller. It's useful to combine multiple
12  interrupt sources into 1 interrupt to parent interrupt controller.
13
14maintainers:
15  - Kevin Chen <kevin_chen@aspeedtech.com>
16
17properties:
18  compatible:
19    enum:
20      - aspeed,ast2700-intc-ic
21
22  reg:
23    maxItems: 1
24
25  interrupt-controller: true
26
27  '#interrupt-cells':
28    const: 1
29    description:
30      The first cell is the IRQ number, the second cell is the trigger
31      type as defined in interrupt.txt in this directory.
32
33  interrupts:
34    minItems: 1
35    maxItems: 10
36    description: |
37      Depend to which INTC0 or INTC1 used.
38      INTC0 and INTC1 are two kinds of interrupt controller with enable and raw
39      status registers for use.
40      INTC0 is used to assert GIC if interrupt in INTC1 asserted.
41      INTC1 is used to assert INTC0 if interrupt of modules asserted.
42      +-----+   +-------+     +---------+---module0
43      | GIC |---| INTC0 |--+--| INTC1_0 |---module2
44      |     |   |       |  |  |         |---...
45      +-----+   +-------+  |  +---------+---module31
46                           |
47                           |   +---------+---module0
48                           +---| INTC1_1 |---module2
49                           |   |         |---...
50                           |   +---------+---module31
51                          ...
52                           |   +---------+---module0
53                           +---| INTC1_5 |---module2
54                               |         |---...
55                               +---------+---module31
56
57required:
58  - compatible
59  - reg
60  - interrupt-controller
61  - '#interrupt-cells'
62  - interrupts
63
64additionalProperties: false
65
66examples:
67  - |
68    #include <dt-bindings/interrupt-controller/arm-gic.h>
69
70    bus {
71        #address-cells = <2>;
72        #size-cells = <2>;
73
74        interrupt-controller@12101b00 {
75            compatible = "aspeed,ast2700-intc-ic";
76            reg = <0 0x12101b00 0 0x10>;
77            #interrupt-cells = <1>;
78            interrupt-controller;
79            interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
80                         <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
81                         <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
82                         <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
83                         <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
84                         <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
85                         <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
86                         <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
87                         <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
88                         <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
89        };
90    };
91