xref: /linux/Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.yaml (revision bf373e4c786bfe989e637195252698f45b157a68)
1*3151c26cSRob Herring (Arm)# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*3151c26cSRob Herring (Arm)%YAML 1.2
3*3151c26cSRob Herring (Arm)---
4*3151c26cSRob Herring (Arm)$id: http://devicetree.org/schemas/interrupt-controller/arm,versatile-fpga-irq.yaml#
5*3151c26cSRob Herring (Arm)$schema: http://devicetree.org/meta-schemas/core.yaml#
6*3151c26cSRob Herring (Arm)
7*3151c26cSRob Herring (Arm)title: ARM Versatile FPGA IRQ Controller
8*3151c26cSRob Herring (Arm)
9*3151c26cSRob Herring (Arm)maintainers:
10*3151c26cSRob Herring (Arm)  - Linus Walleij <linus.walleij@linaro.org>
11*3151c26cSRob Herring (Arm)
12*3151c26cSRob Herring (Arm)description:
13*3151c26cSRob Herring (Arm)  One or more FPGA IRQ controllers can be synthesized in an ARM reference board
14*3151c26cSRob Herring (Arm)  such as the Integrator or Versatile family. The output of these different
15*3151c26cSRob Herring (Arm)  controllers are OR:ed together and fed to the CPU tile's IRQ input. Each
16*3151c26cSRob Herring (Arm)  instance can handle up to 32 interrupts.
17*3151c26cSRob Herring (Arm)
18*3151c26cSRob Herring (Arm)properties:
19*3151c26cSRob Herring (Arm)  compatible:
20*3151c26cSRob Herring (Arm)    const: arm,versatile-fpga-irq
21*3151c26cSRob Herring (Arm)
22*3151c26cSRob Herring (Arm)  interrupt-controller: true
23*3151c26cSRob Herring (Arm)
24*3151c26cSRob Herring (Arm)  '#interrupt-cells':
25*3151c26cSRob Herring (Arm)    const: 1
26*3151c26cSRob Herring (Arm)
27*3151c26cSRob Herring (Arm)  reg:
28*3151c26cSRob Herring (Arm)    maxItems: 1
29*3151c26cSRob Herring (Arm)
30*3151c26cSRob Herring (Arm)  clear-mask:
31*3151c26cSRob Herring (Arm)    description: A mask written to clear all IRQs on the controller at boot.
32*3151c26cSRob Herring (Arm)    $ref: /schemas/types.yaml#/definitions/uint32
33*3151c26cSRob Herring (Arm)
34*3151c26cSRob Herring (Arm)  valid-mask:
35*3151c26cSRob Herring (Arm)    description:
36*3151c26cSRob Herring (Arm)      A bit mask determining which interrupts are valid; unused lines are set to 0.
37*3151c26cSRob Herring (Arm)    $ref: /schemas/types.yaml#/definitions/uint32
38*3151c26cSRob Herring (Arm)
39*3151c26cSRob Herring (Arm)  interrupts:
40*3151c26cSRob Herring (Arm)    maxItems: 1
41*3151c26cSRob Herring (Arm)
42*3151c26cSRob Herring (Arm)additionalProperties: false
43*3151c26cSRob Herring (Arm)
44*3151c26cSRob Herring (Arm)required:
45*3151c26cSRob Herring (Arm)  - compatible
46*3151c26cSRob Herring (Arm)  - interrupt-controller
47*3151c26cSRob Herring (Arm)  - '#interrupt-cells'
48*3151c26cSRob Herring (Arm)  - reg
49*3151c26cSRob Herring (Arm)  - clear-mask
50*3151c26cSRob Herring (Arm)  - valid-mask
51*3151c26cSRob Herring (Arm)
52*3151c26cSRob Herring (Arm)examples:
53*3151c26cSRob Herring (Arm)  - |
54*3151c26cSRob Herring (Arm)    interrupt-controller@14000000 {
55*3151c26cSRob Herring (Arm)        compatible = "arm,versatile-fpga-irq";
56*3151c26cSRob Herring (Arm)        #interrupt-cells = <1>;
57*3151c26cSRob Herring (Arm)        interrupt-controller;
58*3151c26cSRob Herring (Arm)        reg = <0x14000000 0x100>;
59*3151c26cSRob Herring (Arm)        clear-mask = <0xffffffff>;
60*3151c26cSRob Herring (Arm)        valid-mask = <0x003fffff>;
61*3151c26cSRob Herring (Arm)    };
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