1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: ARM Generic Interrupt Controller v1 and v2 8 9maintainers: 10 - Marc Zyngier <marc.zyngier@arm.com> 11 12description: |+ 13 ARM SMP cores are often associated with a GIC, providing per processor 14 interrupts (PPI), shared processor interrupts (SPI) and software 15 generated interrupts (SGI). 16 17 Primary GIC is attached directly to the CPU and typically has PPIs and SGIs. 18 Secondary GICs are cascaded into the upward interrupt controller and do not 19 have PPIs or SGIs. 20 21allOf: 22 - $ref: /schemas/interrupt-controller.yaml# 23 24properties: 25 compatible: 26 oneOf: 27 - items: 28 - enum: 29 - arm,arm11mp-gic 30 - arm,cortex-a15-gic 31 - arm,cortex-a7-gic 32 - arm,cortex-a5-gic 33 - arm,cortex-a9-gic 34 - arm,eb11mp-gic 35 - arm,gic-400 36 - arm,pl390 37 - arm,tc11mp-gic 38 - qcom,msm-8660-qgic 39 - qcom,msm-qgic2 40 41 - items: 42 - const: arm,gic-400 43 - enum: 44 - arm,cortex-a15-gic 45 - arm,cortex-a7-gic 46 47 - items: 48 - const: arm,arm1176jzf-devchip-gic 49 - const: arm,arm11mp-gic 50 51 - items: 52 - const: brcm,brahma-b15-gic 53 - const: arm,cortex-a15-gic 54 55 - oneOf: 56 - const: nvidia,tegra210-agic 57 - items: 58 - enum: 59 - nvidia,tegra186-agic 60 - nvidia,tegra194-agic 61 - const: nvidia,tegra210-agic 62 63 interrupt-controller: true 64 65 "#address-cells": 66 enum: [ 0, 1 ] 67 "#size-cells": 68 const: 1 69 70 "#interrupt-cells": 71 const: 3 72 description: | 73 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI 74 interrupts. 75 76 The 2nd cell contains the interrupt number for the interrupt type. 77 SPI interrupts are in the range [0-987]. PPI interrupts are in the 78 range [0-15]. 79 80 The 3rd cell is the flags, encoded as follows: 81 bits[3:0] trigger type and level flags. 82 1 = low-to-high edge triggered 83 2 = high-to-low edge triggered (invalid for SPIs) 84 4 = active high level-sensitive 85 8 = active low level-sensitive (invalid for SPIs). 86 bits[15:8] PPI interrupt cpu mask. Each bit corresponds to each of 87 the 8 possible cpus attached to the GIC. A bit set to '1' indicated 88 the interrupt is wired to that CPU. Only valid for PPI interrupts. 89 Also note that the configurability of PPI interrupts is IMPLEMENTATION 90 DEFINED and as such not guaranteed to be present (most SoC available 91 in 2014 seem to ignore the setting of this flag and use the hardware 92 default value). 93 94 reg: 95 description: | 96 Specifies base physical address(s) and size of the GIC registers. The 97 first region is the GIC distributor register base and size. The 2nd region 98 is the GIC cpu interface register base and size. 99 100 For GICv2 with virtualization extensions, additional regions are 101 required for specifying the base physical address and size of the VGIC 102 registers. The first additional region is the GIC virtual interface 103 control register base and size. The 2nd additional region is the GIC 104 virtual cpu interface register base and size. 105 minItems: 2 106 maxItems: 4 107 108 ranges: true 109 110 interrupts: 111 description: Interrupt source of the parent interrupt controller on 112 secondary GICs, or VGIC maintenance interrupt on primary GIC (see 113 below). 114 maxItems: 1 115 116 cpu-offset: 117 description: per-cpu offset within the distributor and cpu interface 118 regions, used when the GIC doesn't have banked registers. The offset 119 is cpu-offset * cpu-nr. 120 $ref: /schemas/types.yaml#/definitions/uint32 121 122 clocks: 123 minItems: 1 124 maxItems: 2 125 126 clock-names: 127 description: List of names for the GIC clock input(s). Valid clock names 128 depend on the GIC variant. 129 oneOf: 130 - const: ic_clk # for "arm,arm11mp-gic" 131 - const: PERIPHCLKEN # for "arm,cortex-a15-gic" 132 - items: # for "arm,cortex-a9-gic" 133 - const: PERIPHCLK 134 - const: PERIPHCLKEN 135 - const: clk # for "arm,gic-400" and "nvidia,tegra210" 136 - const: gclk #for "arm,pl390" 137 138 power-domains: 139 maxItems: 1 140 141 resets: 142 maxItems: 1 143 144required: 145 - compatible 146 - reg 147 148patternProperties: 149 "^v2m@[0-9a-f]+$": 150 type: object 151 description: | 152 * GICv2m extension for MSI/MSI-x support (Optional) 153 154 Certain revisions of GIC-400 supports MSI/MSI-x via V2M register frame(s). 155 This is enabled by specifying v2m sub-node(s). 156 157 properties: 158 compatible: 159 const: arm,gic-v2m-frame 160 161 msi-controller: true 162 163 reg: 164 maxItems: 1 165 description: GICv2m MSI interface register base and size 166 167 arm,msi-base-spi: 168 description: When the MSI_TYPER register contains an incorrect value, 169 this property should contain the SPI base of the MSI frame, overriding 170 the HW value. 171 $ref: /schemas/types.yaml#/definitions/uint32 172 173 arm,msi-num-spis: 174 description: When the MSI_TYPER register contains an incorrect value, 175 this property should contain the number of SPIs assigned to the 176 frame, overriding the HW value. 177 $ref: /schemas/types.yaml#/definitions/uint32 178 179 required: 180 - compatible 181 - msi-controller 182 - reg 183 184 additionalProperties: false 185 186additionalProperties: false 187 188examples: 189 - | 190 // GICv1 191 intc: interrupt-controller@fff11000 { 192 compatible = "arm,cortex-a9-gic"; 193 #interrupt-cells = <3>; 194 #address-cells = <1>; 195 interrupt-controller; 196 reg = <0xfff11000 0x1000>, 197 <0xfff10100 0x100>; 198 }; 199 200 - | 201 // GICv2 202 interrupt-controller@2c001000 { 203 compatible = "arm,cortex-a15-gic"; 204 #interrupt-cells = <3>; 205 interrupt-controller; 206 reg = <0x2c001000 0x1000>, 207 <0x2c002000 0x2000>, 208 <0x2c004000 0x2000>, 209 <0x2c006000 0x2000>; 210 interrupts = <1 9 0xf04>; 211 }; 212 213 - | 214 // GICv2m extension for MSI/MSI-x support 215 interrupt-controller@e1101000 { 216 compatible = "arm,gic-400"; 217 #interrupt-cells = <3>; 218 #address-cells = <1>; 219 #size-cells = <1>; 220 interrupt-controller; 221 interrupts = <1 8 0xf04>; 222 ranges = <0 0xe1100000 0x100000>; 223 reg = <0xe1110000 0x01000>, 224 <0xe112f000 0x02000>, 225 <0xe1140000 0x10000>, 226 <0xe1160000 0x10000>; 227 228 v2m0: v2m@80000 { 229 compatible = "arm,gic-v2m-frame"; 230 msi-controller; 231 reg = <0x80000 0x1000>; 232 }; 233 234 //... 235 236 v2mN: v2m@90000 { 237 compatible = "arm,gic-v2m-frame"; 238 msi-controller; 239 reg = <0x90000 0x1000>; 240 }; 241 }; 242... 243