1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: ARM Generic Interrupt Controller v1 and v2 8 9maintainers: 10 - Marc Zyngier <marc.zyngier@arm.com> 11 12description: |+ 13 ARM SMP cores are often associated with a GIC, providing per processor 14 interrupts (PPI), shared processor interrupts (SPI) and software 15 generated interrupts (SGI). 16 17 Primary GIC is attached directly to the CPU and typically has PPIs and SGIs. 18 Secondary GICs are cascaded into the upward interrupt controller and do not 19 have PPIs or SGIs. 20 21allOf: 22 - $ref: /schemas/interrupt-controller.yaml# 23 24properties: 25 compatible: 26 oneOf: 27 - items: 28 - enum: 29 - arm,arm11mp-gic 30 - arm,cortex-a15-gic 31 - arm,cortex-a7-gic 32 - arm,cortex-a5-gic 33 - arm,cortex-a9-gic 34 - arm,eb11mp-gic 35 - arm,gic-400 36 - arm,pl390 37 - arm,tc11mp-gic 38 - qcom,msm-8660-qgic 39 - qcom,msm-qgic2 40 41 - items: 42 - const: arm,gic-400 43 - enum: 44 - arm,cortex-a15-gic 45 - arm,cortex-a7-gic 46 47 - items: 48 - const: arm,arm1176jzf-devchip-gic 49 - const: arm,arm11mp-gic 50 51 - items: 52 - const: brcm,brahma-b15-gic 53 - const: arm,cortex-a15-gic 54 55 - oneOf: 56 - const: nvidia,tegra210-agic 57 - items: 58 - enum: 59 - nvidia,tegra186-agic 60 - nvidia,tegra194-agic 61 - nvidia,tegra234-agic 62 - nvidia,tegra264-agic 63 - const: nvidia,tegra210-agic 64 65 interrupt-controller: true 66 67 "#address-cells": 68 enum: [ 0, 1, 2 ] 69 "#size-cells": 70 enum: [ 1, 2 ] 71 72 "#interrupt-cells": 73 const: 3 74 description: | 75 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI 76 interrupts. 77 78 The 2nd cell contains the interrupt number for the interrupt type. 79 SPI interrupts are in the range [0-987]. PPI interrupts are in the 80 range [0-15]. 81 82 The 3rd cell is the flags, encoded as follows: 83 bits[3:0] trigger type and level flags. 84 1 = low-to-high edge triggered 85 2 = high-to-low edge triggered (invalid for SPIs) 86 4 = active high level-sensitive 87 8 = active low level-sensitive (invalid for SPIs). 88 bits[15:8] PPI interrupt cpu mask. Each bit corresponds to each of 89 the 8 possible cpus attached to the GIC. A bit set to '1' indicated 90 the interrupt is wired to that CPU. Only valid for PPI interrupts. 91 Also note that the configurability of PPI interrupts is IMPLEMENTATION 92 DEFINED and as such not guaranteed to be present (most SoC available 93 in 2014 seem to ignore the setting of this flag and use the hardware 94 default value). 95 96 reg: 97 description: | 98 Specifies base physical address(s) and size of the GIC registers. The 99 first region is the GIC distributor register base and size. The 2nd region 100 is the GIC cpu interface register base and size. 101 102 For GICv2 with virtualization extensions, additional regions are 103 required for specifying the base physical address and size of the VGIC 104 registers. The first additional region is the GIC virtual interface 105 control register base and size. The 2nd additional region is the GIC 106 virtual cpu interface register base and size. 107 minItems: 2 108 maxItems: 4 109 110 ranges: true 111 112 interrupts: 113 description: Interrupt source of the parent interrupt controller on 114 secondary GICs, or VGIC maintenance interrupt on primary GIC (see "GICv2 115 with virtualization extensions" paragraph in the "reg" property). 116 maxItems: 1 117 118 cpu-offset: 119 description: per-cpu offset within the distributor and cpu interface 120 regions, used when the GIC doesn't have banked registers. The offset 121 is cpu-offset * cpu-nr. 122 $ref: /schemas/types.yaml#/definitions/uint32 123 124 clocks: 125 minItems: 1 126 maxItems: 2 127 128 clock-names: 129 description: List of names for the GIC clock input(s). Valid clock names 130 depend on the GIC variant. 131 oneOf: 132 - const: ic_clk # for "arm,arm11mp-gic" 133 - const: PERIPHCLKEN # for "arm,cortex-a15-gic" 134 - items: # for "arm,cortex-a9-gic" 135 - const: PERIPHCLK 136 - const: PERIPHCLKEN 137 - const: clk # for "arm,gic-400" and "nvidia,tegra210" 138 - const: gclk # for "arm,pl390" 139 140 power-domains: 141 maxItems: 1 142 143 resets: 144 maxItems: 1 145 146required: 147 - compatible 148 - reg 149 150patternProperties: 151 "^v2m@[0-9a-f]+$": 152 type: object 153 description: | 154 * GICv2m extension for MSI/MSI-x support (Optional) 155 156 Certain revisions of GIC-400 supports MSI/MSI-x via V2M register frame(s). 157 This is enabled by specifying v2m sub-node(s). 158 159 properties: 160 compatible: 161 const: arm,gic-v2m-frame 162 163 msi-controller: true 164 165 reg: 166 maxItems: 1 167 description: GICv2m MSI interface register base and size 168 169 arm,msi-base-spi: 170 description: When the MSI_TYPER register contains an incorrect value, 171 this property should contain the SPI base of the MSI frame, overriding 172 the HW value. 173 $ref: /schemas/types.yaml#/definitions/uint32 174 175 arm,msi-num-spis: 176 description: When the MSI_TYPER register contains an incorrect value, 177 this property should contain the number of SPIs assigned to the 178 frame, overriding the HW value. 179 $ref: /schemas/types.yaml#/definitions/uint32 180 181 required: 182 - compatible 183 - msi-controller 184 - reg 185 186 additionalProperties: false 187 188additionalProperties: false 189 190examples: 191 - | 192 // GICv1 193 intc: interrupt-controller@fff11000 { 194 compatible = "arm,cortex-a9-gic"; 195 #interrupt-cells = <3>; 196 #address-cells = <1>; 197 interrupt-controller; 198 reg = <0xfff11000 0x1000>, 199 <0xfff10100 0x100>; 200 }; 201 202 - | 203 // GICv2 204 interrupt-controller@2c001000 { 205 compatible = "arm,cortex-a15-gic"; 206 #interrupt-cells = <3>; 207 interrupt-controller; 208 reg = <0x2c001000 0x1000>, 209 <0x2c002000 0x2000>, 210 <0x2c004000 0x2000>, 211 <0x2c006000 0x2000>; 212 interrupts = <1 9 0xf04>; 213 }; 214 215 - | 216 // GICv2m extension for MSI/MSI-x support 217 interrupt-controller@e1101000 { 218 compatible = "arm,gic-400"; 219 #interrupt-cells = <3>; 220 #address-cells = <1>; 221 #size-cells = <1>; 222 interrupt-controller; 223 interrupts = <1 8 0xf04>; 224 ranges = <0 0xe1100000 0x100000>; 225 reg = <0xe1110000 0x01000>, 226 <0xe112f000 0x02000>, 227 <0xe1140000 0x10000>, 228 <0xe1160000 0x10000>; 229 230 v2m0: v2m@80000 { 231 compatible = "arm,gic-v2m-frame"; 232 msi-controller; 233 reg = <0x80000 0x1000>; 234 }; 235 236 //... 237 238 v2mN: v2m@90000 { 239 compatible = "arm,gic-v2m-frame"; 240 msi-controller; 241 reg = <0x90000 0x1000>; 242 }; 243 }; 244... 245