1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v5-iwb.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: ARM Generic Interrupt Controller, version 5 Interrupt Wire Bridge (IWB) 8 9maintainers: 10 - Lorenzo Pieralisi <lpieralisi@kernel.org> 11 - Marc Zyngier <maz@kernel.org> 12 13description: | 14 The GICv5 architecture defines the guidelines to implement GICv5 15 compliant interrupt controllers for AArch64 systems. 16 17 The GICv5 specification can be found at 18 https://developer.arm.com/documentation/aes0070 19 20 GICv5 has zero or more Interrupt Wire Bridges (IWB) that are responsible 21 for translating wire signals into interrupt messages to the GICv5 ITS. 22 23allOf: 24 - $ref: /schemas/interrupt-controller.yaml# 25 26properties: 27 compatible: 28 const: arm,gic-v5-iwb 29 30 reg: 31 items: 32 - description: IWB control frame 33 34 "#address-cells": 35 const: 0 36 37 "#interrupt-cells": 38 description: | 39 The 1st cell corresponds to the IWB wire. 40 41 The 2nd cell is the flags, encoded as follows: 42 bits[3:0] trigger type and level flags. 43 44 1 = low-to-high edge triggered 45 2 = high-to-low edge triggered 46 4 = active high level-sensitive 47 8 = active low level-sensitive 48 49 const: 2 50 51 interrupt-controller: true 52 53 msi-parent: 54 maxItems: 1 55 56required: 57 - compatible 58 - reg 59 - "#interrupt-cells" 60 - interrupt-controller 61 - msi-parent 62 63additionalProperties: false 64 65examples: 66 - | 67 interrupt-controller@2f000000 { 68 compatible = "arm,gic-v5-iwb"; 69 reg = <0x2f000000 0x10000>; 70 71 #address-cells = <0>; 72 73 #interrupt-cells = <2>; 74 interrupt-controller; 75 76 msi-parent = <&its0 64>; 77 }; 78... 79