1*7d7299bdSLorenzo Pieralisi# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*7d7299bdSLorenzo Pieralisi%YAML 1.2 3*7d7299bdSLorenzo Pieralisi--- 4*7d7299bdSLorenzo Pieralisi$id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v5-iwb.yaml# 5*7d7299bdSLorenzo Pieralisi$schema: http://devicetree.org/meta-schemas/core.yaml# 6*7d7299bdSLorenzo Pieralisi 7*7d7299bdSLorenzo Pieralisititle: ARM Generic Interrupt Controller, version 5 Interrupt Wire Bridge (IWB) 8*7d7299bdSLorenzo Pieralisi 9*7d7299bdSLorenzo Pieralisimaintainers: 10*7d7299bdSLorenzo Pieralisi - Lorenzo Pieralisi <lpieralisi@kernel.org> 11*7d7299bdSLorenzo Pieralisi - Marc Zyngier <maz@kernel.org> 12*7d7299bdSLorenzo Pieralisi 13*7d7299bdSLorenzo Pieralisidescription: | 14*7d7299bdSLorenzo Pieralisi The GICv5 architecture defines the guidelines to implement GICv5 15*7d7299bdSLorenzo Pieralisi compliant interrupt controllers for AArch64 systems. 16*7d7299bdSLorenzo Pieralisi 17*7d7299bdSLorenzo Pieralisi The GICv5 specification can be found at 18*7d7299bdSLorenzo Pieralisi https://developer.arm.com/documentation/aes0070 19*7d7299bdSLorenzo Pieralisi 20*7d7299bdSLorenzo Pieralisi GICv5 has zero or more Interrupt Wire Bridges (IWB) that are responsible 21*7d7299bdSLorenzo Pieralisi for translating wire signals into interrupt messages to the GICv5 ITS. 22*7d7299bdSLorenzo Pieralisi 23*7d7299bdSLorenzo PieralisiallOf: 24*7d7299bdSLorenzo Pieralisi - $ref: /schemas/interrupt-controller.yaml# 25*7d7299bdSLorenzo Pieralisi 26*7d7299bdSLorenzo Pieralisiproperties: 27*7d7299bdSLorenzo Pieralisi compatible: 28*7d7299bdSLorenzo Pieralisi const: arm,gic-v5-iwb 29*7d7299bdSLorenzo Pieralisi 30*7d7299bdSLorenzo Pieralisi reg: 31*7d7299bdSLorenzo Pieralisi items: 32*7d7299bdSLorenzo Pieralisi - description: IWB control frame 33*7d7299bdSLorenzo Pieralisi 34*7d7299bdSLorenzo Pieralisi "#address-cells": 35*7d7299bdSLorenzo Pieralisi const: 0 36*7d7299bdSLorenzo Pieralisi 37*7d7299bdSLorenzo Pieralisi "#interrupt-cells": 38*7d7299bdSLorenzo Pieralisi description: | 39*7d7299bdSLorenzo Pieralisi The 1st cell corresponds to the IWB wire. 40*7d7299bdSLorenzo Pieralisi 41*7d7299bdSLorenzo Pieralisi The 2nd cell is the flags, encoded as follows: 42*7d7299bdSLorenzo Pieralisi bits[3:0] trigger type and level flags. 43*7d7299bdSLorenzo Pieralisi 44*7d7299bdSLorenzo Pieralisi 1 = low-to-high edge triggered 45*7d7299bdSLorenzo Pieralisi 2 = high-to-low edge triggered 46*7d7299bdSLorenzo Pieralisi 4 = active high level-sensitive 47*7d7299bdSLorenzo Pieralisi 8 = active low level-sensitive 48*7d7299bdSLorenzo Pieralisi 49*7d7299bdSLorenzo Pieralisi const: 2 50*7d7299bdSLorenzo Pieralisi 51*7d7299bdSLorenzo Pieralisi interrupt-controller: true 52*7d7299bdSLorenzo Pieralisi 53*7d7299bdSLorenzo Pieralisi msi-parent: 54*7d7299bdSLorenzo Pieralisi maxItems: 1 55*7d7299bdSLorenzo Pieralisi 56*7d7299bdSLorenzo Pieralisirequired: 57*7d7299bdSLorenzo Pieralisi - compatible 58*7d7299bdSLorenzo Pieralisi - reg 59*7d7299bdSLorenzo Pieralisi - "#interrupt-cells" 60*7d7299bdSLorenzo Pieralisi - interrupt-controller 61*7d7299bdSLorenzo Pieralisi - msi-parent 62*7d7299bdSLorenzo Pieralisi 63*7d7299bdSLorenzo PieralisiadditionalProperties: false 64*7d7299bdSLorenzo Pieralisi 65*7d7299bdSLorenzo Pieralisiexamples: 66*7d7299bdSLorenzo Pieralisi - | 67*7d7299bdSLorenzo Pieralisi interrupt-controller@2f000000 { 68*7d7299bdSLorenzo Pieralisi compatible = "arm,gic-v5-iwb"; 69*7d7299bdSLorenzo Pieralisi reg = <0x2f000000 0x10000>; 70*7d7299bdSLorenzo Pieralisi 71*7d7299bdSLorenzo Pieralisi #address-cells = <0>; 72*7d7299bdSLorenzo Pieralisi 73*7d7299bdSLorenzo Pieralisi #interrupt-cells = <2>; 74*7d7299bdSLorenzo Pieralisi interrupt-controller; 75*7d7299bdSLorenzo Pieralisi 76*7d7299bdSLorenzo Pieralisi msi-parent = <&its0 64>; 77*7d7299bdSLorenzo Pieralisi }; 78*7d7299bdSLorenzo Pieralisi... 79