1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: ARM Generic Interrupt Controller, version 3 8 9maintainers: 10 - Marc Zyngier <maz@kernel.org> 11 12description: | 13 AArch64 SMP cores are often associated with a GICv3, providing Private 14 Peripheral Interrupts (PPI), Shared Peripheral Interrupts (SPI), 15 Software Generated Interrupts (SGI), and Locality-specific Peripheral 16 Interrupts (LPI). 17 18allOf: 19 - $ref: /schemas/interrupt-controller.yaml# 20 21properties: 22 compatible: 23 oneOf: 24 - items: 25 - enum: 26 - qcom,msm8996-gic-v3 27 - const: arm,gic-v3 28 - const: arm,gic-v3 29 30 interrupt-controller: true 31 32 "#address-cells": 33 enum: [ 0, 1, 2 ] 34 "#size-cells": 35 enum: [ 1, 2 ] 36 37 ranges: true 38 39 "#interrupt-cells": 40 description: | 41 Specifies the number of cells needed to encode an interrupt source. 42 Must be a single cell with a value of at least 3. 43 If the system requires describing PPI affinity, then the value must 44 be at least 4. 45 46 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI 47 interrupts, 2 for interrupts in the Extended SPI range, 3 for the 48 Extended PPI range. Other values are reserved for future use. 49 50 The 2nd cell contains the interrupt number for the interrupt type. 51 SPI interrupts are in the range [0-987]. PPI interrupts are in the 52 range [0-15]. Extended SPI interrupts are in the range [0-1023]. 53 Extended PPI interrupts are in the range [0-127]. 54 55 The 3rd cell is the flags, encoded as follows: 56 bits[3:0] trigger type and level flags. 57 1 = edge triggered 58 4 = level triggered 59 60 The 4th cell is a phandle to a node describing a set of CPUs this 61 interrupt is affine to. The interrupt must be a PPI, and the node 62 pointed must be a subnode of the "ppi-partitions" subnode. For 63 interrupt types other than PPI or PPIs that are not partitioned, 64 this cell must be zero. See the "ppi-partitions" node description 65 below. 66 67 Cells 5 and beyond are reserved for future use and must have a value 68 of 0 if present. 69 enum: [ 3, 4 ] 70 71 reg: 72 description: | 73 Specifies base physical address(s) and size of the GIC 74 registers, in the following order: 75 - GIC Distributor interface (GICD) 76 - GIC Redistributors (GICR), one range per redistributor region 77 - GIC CPU interface (GICC) 78 - GIC Hypervisor interface (GICH) 79 - GIC Virtual CPU interface (GICV) 80 81 GICC, GICH and GICV are optional, but must be described if the CPUs 82 support them. Examples of such CPUs are ARM's implementations of the 83 ARMv8.0 architecture such as Cortex-A32, A34, A35, A53, A57, A72 and 84 A73 (this list is not exhaustive). 85 86 minItems: 2 87 maxItems: 4096 # Should be enough? 88 89 interrupts: 90 description: 91 Interrupt source of the VGIC maintenance interrupt. 92 maxItems: 1 93 94 redistributor-stride: 95 description: 96 If using padding pages, specifies the stride of consecutive 97 redistributors. Must be a multiple of 64kB. 98 $ref: /schemas/types.yaml#/definitions/uint64 99 multipleOf: 0x10000 100 exclusiveMinimum: 0 101 102 "#redistributor-regions": 103 description: 104 The number of independent contiguous regions occupied by the 105 redistributors. Required if more than one such region is present. 106 $ref: /schemas/types.yaml#/definitions/uint32 107 maximum: 4096 108 109 dma-noncoherent: 110 description: 111 Present if the GIC redistributors permit programming shareability 112 and cacheability attributes but are connected to a non-coherent 113 downstream interconnect. 114 115 msi-controller: 116 description: 117 Only present if the Message Based Interrupt functionality is 118 being exposed by the HW, and the mbi-ranges property present. 119 120 mbi-ranges: 121 description: 122 A list of pairs <intid span>, where "intid" is the first SPI of a range 123 that can be used an MBI, and "span" the size of that range. Multiple 124 ranges can be provided. 125 $ref: /schemas/types.yaml#/definitions/uint32-matrix 126 items: 127 minItems: 2 128 maxItems: 2 129 130 mbi-alias: 131 description: 132 Address property. Base address of an alias of the GICD region containing 133 only the {SET,CLR}SPI registers to be used if isolation is required, 134 and if supported by the HW. 135 oneOf: 136 - $ref: /schemas/types.yaml#/definitions/uint32 137 - $ref: /schemas/types.yaml#/definitions/uint64 138 139 ppi-partitions: 140 type: object 141 additionalProperties: false 142 description: 143 PPI affinity can be expressed as a single "ppi-partitions" node, 144 containing a set of sub-nodes. 145 patternProperties: 146 "^interrupt-partition-[0-9]+$": 147 type: object 148 additionalProperties: false 149 properties: 150 affinity: 151 $ref: /schemas/types.yaml#/definitions/phandle-array 152 items: 153 maxItems: 1 154 description: 155 Should be a list of phandles to CPU nodes (as described in 156 Documentation/devicetree/bindings/arm/cpus.yaml). 157 158 required: 159 - affinity 160 161 clocks: 162 maxItems: 1 163 164 clock-names: 165 items: 166 - const: aclk 167 168 power-domains: 169 maxItems: 1 170 171 resets: 172 maxItems: 1 173 174 mediatek,broken-save-restore-fw: 175 type: boolean 176 description: 177 Asserts that the firmware on this device has issues saving and restoring 178 GICR registers when the GIC redistributors are powered off. 179 180dependencies: 181 mbi-ranges: [ msi-controller ] 182 msi-controller: [ mbi-ranges ] 183 184required: 185 - compatible 186 - reg 187 188patternProperties: 189 "^gic-its@": false 190 "^interrupt-controller@[0-9a-f]+$": false 191 # msi-controller is preferred, but allow other names 192 "^(msi-controller|gic-its|interrupt-controller)@[0-9a-f]+$": 193 type: object 194 description: 195 GICv3 has one or more Interrupt Translation Services (ITS) that are 196 used to route Message Signalled Interrupts (MSI) to the CPUs. 197 properties: 198 compatible: 199 const: arm,gic-v3-its 200 201 dma-noncoherent: 202 description: 203 Present if the GIC ITS permits programming shareability and 204 cacheability attributes but is connected to a non-coherent 205 downstream interconnect. 206 207 msi-controller: true 208 209 "#msi-cells": 210 description: 211 The single msi-cell is the DeviceID of the device which will generate 212 the MSI. 213 const: 1 214 215 reg: 216 description: 217 Specifies the base physical address and size of the ITS registers. 218 maxItems: 1 219 220 socionext,synquacer-pre-its: 221 description: 222 (u32, u32) tuple describing the untranslated 223 address and size of the pre-ITS window. 224 $ref: /schemas/types.yaml#/definitions/uint32-array 225 minItems: 2 226 maxItems: 2 227 228 required: 229 - compatible 230 - msi-controller 231 - "#msi-cells" 232 - reg 233 234 additionalProperties: false 235 236additionalProperties: false 237 238examples: 239 - | 240 gic: interrupt-controller@2cf00000 { 241 compatible = "arm,gic-v3"; 242 #interrupt-cells = <3>; 243 #address-cells = <1>; 244 #size-cells = <1>; 245 ranges; 246 interrupt-controller; 247 reg = <0x2f000000 0x10000>, // GICD 248 <0x2f100000 0x200000>, // GICR 249 <0x2c000000 0x2000>, // GICC 250 <0x2c010000 0x2000>, // GICH 251 <0x2c020000 0x2000>; // GICV 252 interrupts = <1 9 4>; 253 254 msi-controller; 255 mbi-ranges = <256 128>; 256 257 msi-controller@2c200000 { 258 compatible = "arm,gic-v3-its"; 259 msi-controller; 260 #msi-cells = <1>; 261 reg = <0x2c200000 0x20000>; 262 }; 263 }; 264 265 - | 266 interrupt-controller@2c010000 { 267 compatible = "arm,gic-v3"; 268 #interrupt-cells = <4>; 269 #address-cells = <1>; 270 #size-cells = <1>; 271 ranges; 272 interrupt-controller; 273 redistributor-stride = <0x0 0x40000>; // 256kB stride 274 #redistributor-regions = <2>; 275 reg = <0x2c010000 0x10000>, // GICD 276 <0x2d000000 0x800000>, // GICR 1: CPUs 0-31 277 <0x2e000000 0x800000>, // GICR 2: CPUs 32-63 278 <0x2c040000 0x2000>, // GICC 279 <0x2c060000 0x2000>, // GICH 280 <0x2c080000 0x2000>; // GICV 281 interrupts = <1 9 4 0>; 282 283 msi-controller@2c200000 { 284 compatible = "arm,gic-v3-its"; 285 msi-controller; 286 #msi-cells = <1>; 287 reg = <0x2c200000 0x20000>; 288 }; 289 290 msi-controller@2c400000 { 291 compatible = "arm,gic-v3-its"; 292 msi-controller; 293 #msi-cells = <1>; 294 reg = <0x2c400000 0x20000>; 295 }; 296 297 ppi-partitions { 298 part0: interrupt-partition-0 { 299 affinity = <&cpu0>, <&cpu2>; 300 }; 301 302 part1: interrupt-partition-1 { 303 affinity = <&cpu1>, <&cpu3>; 304 }; 305 }; 306 }; 307 308 309 device@0 { 310 reg = <0 4>; 311 interrupts = <1 1 4 &part0>; 312 }; 313 314... 315