1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: ARM Generic Interrupt Controller v1 and v2 8 9maintainers: 10 - Marc Zyngier <marc.zyngier@arm.com> 11 12description: |+ 13 ARM SMP cores are often associated with a GIC, providing per processor 14 interrupts (PPI), shared processor interrupts (SPI) and software 15 generated interrupts (SGI). 16 17 Primary GIC is attached directly to the CPU and typically has PPIs and SGIs. 18 Secondary GICs are cascaded into the upward interrupt controller and do not 19 have PPIs or SGIs. 20 21allOf: 22 - $ref: /schemas/interrupt-controller.yaml# 23 24properties: 25 compatible: 26 oneOf: 27 - items: 28 - enum: 29 - arm,arm11mp-gic 30 - arm,cortex-a15-gic 31 - arm,cortex-a7-gic 32 - arm,cortex-a5-gic 33 - arm,cortex-a9-gic 34 - arm,eb11mp-gic 35 - arm,gic-400 36 - arm,pl390 37 - arm,tc11mp-gic 38 - nvidia,tegra210-agic 39 - qcom,msm-8660-qgic 40 - qcom,msm-qgic2 41 42 - items: 43 - const: arm,gic-400 44 - enum: 45 - arm,cortex-a15-gic 46 - arm,cortex-a7-gic 47 48 - items: 49 - const: arm,arm1176jzf-devchip-gic 50 - const: arm,arm11mp-gic 51 52 - items: 53 - const: brcm,brahma-b15-gic 54 - const: arm,cortex-a15-gic 55 56 interrupt-controller: true 57 58 "#address-cells": 59 enum: [ 0, 1 ] 60 "#size-cells": 61 const: 1 62 63 "#interrupt-cells": 64 const: 3 65 description: | 66 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI 67 interrupts. 68 69 The 2nd cell contains the interrupt number for the interrupt type. 70 SPI interrupts are in the range [0-987]. PPI interrupts are in the 71 range [0-15]. 72 73 The 3rd cell is the flags, encoded as follows: 74 bits[3:0] trigger type and level flags. 75 1 = low-to-high edge triggered 76 2 = high-to-low edge triggered (invalid for SPIs) 77 4 = active high level-sensitive 78 8 = active low level-sensitive (invalid for SPIs). 79 bits[15:8] PPI interrupt cpu mask. Each bit corresponds to each of 80 the 8 possible cpus attached to the GIC. A bit set to '1' indicated 81 the interrupt is wired to that CPU. Only valid for PPI interrupts. 82 Also note that the configurability of PPI interrupts is IMPLEMENTATION 83 DEFINED and as such not guaranteed to be present (most SoC available 84 in 2014 seem to ignore the setting of this flag and use the hardware 85 default value). 86 87 reg: 88 description: | 89 Specifies base physical address(s) and size of the GIC registers. The 90 first region is the GIC distributor register base and size. The 2nd region 91 is the GIC cpu interface register base and size. 92 93 For GICv2 with virtualization extensions, additional regions are 94 required for specifying the base physical address and size of the VGIC 95 registers. The first additional region is the GIC virtual interface 96 control register base and size. The 2nd additional region is the GIC 97 virtual cpu interface register base and size. 98 minItems: 2 99 maxItems: 4 100 101 ranges: true 102 103 interrupts: 104 description: Interrupt source of the parent interrupt controller on 105 secondary GICs, or VGIC maintenance interrupt on primary GIC (see 106 below). 107 maxItems: 1 108 109 cpu-offset: 110 description: per-cpu offset within the distributor and cpu interface 111 regions, used when the GIC doesn't have banked registers. The offset 112 is cpu-offset * cpu-nr. 113 $ref: /schemas/types.yaml#/definitions/uint32 114 115 clocks: 116 minItems: 1 117 maxItems: 2 118 119 clock-names: 120 description: List of names for the GIC clock input(s). Valid clock names 121 depend on the GIC variant. 122 oneOf: 123 - const: ic_clk # for "arm,arm11mp-gic" 124 - const: PERIPHCLKEN # for "arm,cortex-a15-gic" 125 - items: # for "arm,cortex-a9-gic" 126 - const: PERIPHCLK 127 - const: PERIPHCLKEN 128 - const: clk # for "arm,gic-400" and "nvidia,tegra210" 129 - const: gclk #for "arm,pl390" 130 131 power-domains: 132 maxItems: 1 133 134 resets: 135 maxItems: 1 136 137required: 138 - compatible 139 - reg 140 141patternProperties: 142 "^v2m@[0-9a-f]+$": 143 type: object 144 description: | 145 * GICv2m extension for MSI/MSI-x support (Optional) 146 147 Certain revisions of GIC-400 supports MSI/MSI-x via V2M register frame(s). 148 This is enabled by specifying v2m sub-node(s). 149 150 properties: 151 compatible: 152 const: arm,gic-v2m-frame 153 154 msi-controller: true 155 156 reg: 157 maxItems: 1 158 description: GICv2m MSI interface register base and size 159 160 arm,msi-base-spi: 161 description: When the MSI_TYPER register contains an incorrect value, 162 this property should contain the SPI base of the MSI frame, overriding 163 the HW value. 164 $ref: /schemas/types.yaml#/definitions/uint32 165 166 arm,msi-num-spis: 167 description: When the MSI_TYPER register contains an incorrect value, 168 this property should contain the number of SPIs assigned to the 169 frame, overriding the HW value. 170 $ref: /schemas/types.yaml#/definitions/uint32 171 172 required: 173 - compatible 174 - msi-controller 175 - reg 176 177 additionalProperties: false 178 179additionalProperties: false 180 181examples: 182 - | 183 // GICv1 184 intc: interrupt-controller@fff11000 { 185 compatible = "arm,cortex-a9-gic"; 186 #interrupt-cells = <3>; 187 #address-cells = <1>; 188 interrupt-controller; 189 reg = <0xfff11000 0x1000>, 190 <0xfff10100 0x100>; 191 }; 192 193 - | 194 // GICv2 195 interrupt-controller@2c001000 { 196 compatible = "arm,cortex-a15-gic"; 197 #interrupt-cells = <3>; 198 interrupt-controller; 199 reg = <0x2c001000 0x1000>, 200 <0x2c002000 0x2000>, 201 <0x2c004000 0x2000>, 202 <0x2c006000 0x2000>; 203 interrupts = <1 9 0xf04>; 204 }; 205 206 - | 207 // GICv2m extension for MSI/MSI-x support 208 interrupt-controller@e1101000 { 209 compatible = "arm,gic-400"; 210 #interrupt-cells = <3>; 211 #address-cells = <1>; 212 #size-cells = <1>; 213 interrupt-controller; 214 interrupts = <1 8 0xf04>; 215 ranges = <0 0xe1100000 0x100000>; 216 reg = <0xe1110000 0x01000>, 217 <0xe112f000 0x02000>, 218 <0xe1140000 0x10000>, 219 <0xe1160000 0x10000>; 220 221 v2m0: v2m@80000 { 222 compatible = "arm,gic-v2m-frame"; 223 msi-controller; 224 reg = <0x80000 0x1000>; 225 }; 226 227 //... 228 229 v2mN: v2m@90000 { 230 compatible = "arm,gic-v2m-frame"; 231 msi-controller; 232 reg = <0x90000 0x1000>; 233 }; 234 }; 235... 236