166ed144fSRob Herring# SPDX-License-Identifier: GPL-2.0 266ed144fSRob Herring%YAML 1.2 366ed144fSRob Herring--- 466ed144fSRob Herring$id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml# 566ed144fSRob Herring$schema: http://devicetree.org/meta-schemas/core.yaml# 666ed144fSRob Herring 766ed144fSRob Herringtitle: ARM Generic Interrupt Controller v1 and v2 866ed144fSRob Herring 966ed144fSRob Herringmaintainers: 1066ed144fSRob Herring - Marc Zyngier <marc.zyngier@arm.com> 1166ed144fSRob Herring 1266ed144fSRob Herringdescription: |+ 1366ed144fSRob Herring ARM SMP cores are often associated with a GIC, providing per processor 1466ed144fSRob Herring interrupts (PPI), shared processor interrupts (SPI) and software 1566ed144fSRob Herring generated interrupts (SGI). 1666ed144fSRob Herring 1766ed144fSRob Herring Primary GIC is attached directly to the CPU and typically has PPIs and SGIs. 1866ed144fSRob Herring Secondary GICs are cascaded into the upward interrupt controller and do not 1966ed144fSRob Herring have PPIs or SGIs. 2066ed144fSRob Herring 2166ed144fSRob HerringallOf: 2266ed144fSRob Herring - $ref: /schemas/interrupt-controller.yaml# 2366ed144fSRob Herring 2466ed144fSRob Herringproperties: 2566ed144fSRob Herring compatible: 2666ed144fSRob Herring oneOf: 2766ed144fSRob Herring - items: 2866ed144fSRob Herring - enum: 2966ed144fSRob Herring - arm,arm11mp-gic 3066ed144fSRob Herring - arm,cortex-a15-gic 3166ed144fSRob Herring - arm,cortex-a7-gic 3266ed144fSRob Herring - arm,cortex-a5-gic 3366ed144fSRob Herring - arm,cortex-a9-gic 3466ed144fSRob Herring - arm,eb11mp-gic 3566ed144fSRob Herring - arm,gic-400 3666ed144fSRob Herring - arm,pl390 3766ed144fSRob Herring - arm,tc11mp-gic 3866ed144fSRob Herring - nvidia,tegra210-agic 3966ed144fSRob Herring - qcom,msm-8660-qgic 4066ed144fSRob Herring - qcom,msm-qgic2 4166ed144fSRob Herring 4266ed144fSRob Herring - items: 43*61efb56eSAndre Przywara - const: arm,gic-400 44*61efb56eSAndre Przywara - enum: 45*61efb56eSAndre Przywara - arm,cortex-a15-gic 46*61efb56eSAndre Przywara - arm,cortex-a7-gic 47*61efb56eSAndre Przywara 48*61efb56eSAndre Przywara - items: 4966ed144fSRob Herring - const: arm,arm1176jzf-devchip-gic 5066ed144fSRob Herring - const: arm,arm11mp-gic 5166ed144fSRob Herring 5266ed144fSRob Herring - items: 5366ed144fSRob Herring - const: brcm,brahma-b15-gic 5466ed144fSRob Herring - const: arm,cortex-a15-gic 5566ed144fSRob Herring 5666ed144fSRob Herring interrupt-controller: true 5766ed144fSRob Herring 5866ed144fSRob Herring "#address-cells": 5966ed144fSRob Herring enum: [ 0, 1 ] 6066ed144fSRob Herring "#size-cells": 6166ed144fSRob Herring const: 1 6266ed144fSRob Herring 6366ed144fSRob Herring "#interrupt-cells": 6466ed144fSRob Herring const: 3 6566ed144fSRob Herring description: | 6666ed144fSRob Herring The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI 6766ed144fSRob Herring interrupts. 6866ed144fSRob Herring 6966ed144fSRob Herring The 2nd cell contains the interrupt number for the interrupt type. 7066ed144fSRob Herring SPI interrupts are in the range [0-987]. PPI interrupts are in the 7166ed144fSRob Herring range [0-15]. 7266ed144fSRob Herring 7366ed144fSRob Herring The 3rd cell is the flags, encoded as follows: 7466ed144fSRob Herring bits[3:0] trigger type and level flags. 7566ed144fSRob Herring 1 = low-to-high edge triggered 7666ed144fSRob Herring 2 = high-to-low edge triggered (invalid for SPIs) 7766ed144fSRob Herring 4 = active high level-sensitive 7866ed144fSRob Herring 8 = active low level-sensitive (invalid for SPIs). 7966ed144fSRob Herring bits[15:8] PPI interrupt cpu mask. Each bit corresponds to each of 8066ed144fSRob Herring the 8 possible cpus attached to the GIC. A bit set to '1' indicated 8166ed144fSRob Herring the interrupt is wired to that CPU. Only valid for PPI interrupts. 8266ed144fSRob Herring Also note that the configurability of PPI interrupts is IMPLEMENTATION 8366ed144fSRob Herring DEFINED and as such not guaranteed to be present (most SoC available 8466ed144fSRob Herring in 2014 seem to ignore the setting of this flag and use the hardware 8566ed144fSRob Herring default value). 8666ed144fSRob Herring 8766ed144fSRob Herring reg: 8866ed144fSRob Herring description: | 8966ed144fSRob Herring Specifies base physical address(s) and size of the GIC registers. The 9066ed144fSRob Herring first region is the GIC distributor register base and size. The 2nd region 9166ed144fSRob Herring is the GIC cpu interface register base and size. 9266ed144fSRob Herring 9366ed144fSRob Herring For GICv2 with virtualization extensions, additional regions are 9466ed144fSRob Herring required for specifying the base physical address and size of the VGIC 9566ed144fSRob Herring registers. The first additional region is the GIC virtual interface 9666ed144fSRob Herring control register base and size. The 2nd additional region is the GIC 9766ed144fSRob Herring virtual cpu interface register base and size. 9866ed144fSRob Herring minItems: 2 9966ed144fSRob Herring maxItems: 4 10066ed144fSRob Herring 1018d665693SRob Herring ranges: true 1028d665693SRob Herring 10366ed144fSRob Herring interrupts: 10466ed144fSRob Herring description: Interrupt source of the parent interrupt controller on 10566ed144fSRob Herring secondary GICs, or VGIC maintenance interrupt on primary GIC (see 10666ed144fSRob Herring below). 10766ed144fSRob Herring maxItems: 1 10866ed144fSRob Herring 10966ed144fSRob Herring cpu-offset: 11066ed144fSRob Herring description: per-cpu offset within the distributor and cpu interface 11166ed144fSRob Herring regions, used when the GIC doesn't have banked registers. The offset 11266ed144fSRob Herring is cpu-offset * cpu-nr. 11366ed144fSRob Herring $ref: /schemas/types.yaml#/definitions/uint32 11466ed144fSRob Herring 11566ed144fSRob Herring clocks: 11666ed144fSRob Herring minItems: 1 11766ed144fSRob Herring maxItems: 2 11866ed144fSRob Herring 11966ed144fSRob Herring clock-names: 12066ed144fSRob Herring description: List of names for the GIC clock input(s). Valid clock names 12166ed144fSRob Herring depend on the GIC variant. 12266ed144fSRob Herring oneOf: 12366ed144fSRob Herring - const: ic_clk # for "arm,arm11mp-gic" 12466ed144fSRob Herring - const: PERIPHCLKEN # for "arm,cortex-a15-gic" 12566ed144fSRob Herring - items: # for "arm,cortex-a9-gic" 12666ed144fSRob Herring - const: PERIPHCLK 12766ed144fSRob Herring - const: PERIPHCLKEN 12866ed144fSRob Herring - const: clk # for "arm,gic-400" and "nvidia,tegra210" 12966ed144fSRob Herring - const: gclk #for "arm,pl390" 13066ed144fSRob Herring 13166ed144fSRob Herring power-domains: 13266ed144fSRob Herring maxItems: 1 13366ed144fSRob Herring 13466ed144fSRob Herringrequired: 13566ed144fSRob Herring - compatible 13666ed144fSRob Herring - reg 13766ed144fSRob Herring 13866ed144fSRob HerringpatternProperties: 13966ed144fSRob Herring "^v2m@[0-9a-f]+$": 14099838f01SRob Herring type: object 14166ed144fSRob Herring description: | 14266ed144fSRob Herring * GICv2m extension for MSI/MSI-x support (Optional) 14366ed144fSRob Herring 14466ed144fSRob Herring Certain revisions of GIC-400 supports MSI/MSI-x via V2M register frame(s). 14566ed144fSRob Herring This is enabled by specifying v2m sub-node(s). 14666ed144fSRob Herring 14766ed144fSRob Herring properties: 14866ed144fSRob Herring compatible: 14966ed144fSRob Herring const: arm,gic-v2m-frame 15066ed144fSRob Herring 15166ed144fSRob Herring msi-controller: true 15266ed144fSRob Herring 15366ed144fSRob Herring reg: 15466ed144fSRob Herring maxItems: 1 15566ed144fSRob Herring description: GICv2m MSI interface register base and size 15666ed144fSRob Herring 15766ed144fSRob Herring arm,msi-base-spi: 15866ed144fSRob Herring description: When the MSI_TYPER register contains an incorrect value, 15966ed144fSRob Herring this property should contain the SPI base of the MSI frame, overriding 16066ed144fSRob Herring the HW value. 16166ed144fSRob Herring $ref: /schemas/types.yaml#/definitions/uint32 16266ed144fSRob Herring 16366ed144fSRob Herring arm,msi-num-spis: 16466ed144fSRob Herring description: When the MSI_TYPER register contains an incorrect value, 16566ed144fSRob Herring this property should contain the number of SPIs assigned to the 16666ed144fSRob Herring frame, overriding the HW value. 16766ed144fSRob Herring $ref: /schemas/types.yaml#/definitions/uint32 16866ed144fSRob Herring 16966ed144fSRob Herring required: 17066ed144fSRob Herring - compatible 17166ed144fSRob Herring - msi-controller 17266ed144fSRob Herring - reg 17366ed144fSRob Herring 17466ed144fSRob Herring additionalProperties: false 17566ed144fSRob Herring 17666ed144fSRob HerringadditionalProperties: false 17766ed144fSRob Herring 17866ed144fSRob Herringexamples: 17966ed144fSRob Herring - | 18066ed144fSRob Herring // GICv1 18166ed144fSRob Herring intc: interrupt-controller@fff11000 { 18266ed144fSRob Herring compatible = "arm,cortex-a9-gic"; 18366ed144fSRob Herring #interrupt-cells = <3>; 18466ed144fSRob Herring #address-cells = <1>; 18566ed144fSRob Herring interrupt-controller; 18666ed144fSRob Herring reg = <0xfff11000 0x1000>, 18766ed144fSRob Herring <0xfff10100 0x100>; 18866ed144fSRob Herring }; 18966ed144fSRob Herring 19066ed144fSRob Herring - | 19166ed144fSRob Herring // GICv2 19266ed144fSRob Herring interrupt-controller@2c001000 { 19366ed144fSRob Herring compatible = "arm,cortex-a15-gic"; 19466ed144fSRob Herring #interrupt-cells = <3>; 19566ed144fSRob Herring interrupt-controller; 19666ed144fSRob Herring reg = <0x2c001000 0x1000>, 19766ed144fSRob Herring <0x2c002000 0x2000>, 19866ed144fSRob Herring <0x2c004000 0x2000>, 19966ed144fSRob Herring <0x2c006000 0x2000>; 20066ed144fSRob Herring interrupts = <1 9 0xf04>; 20166ed144fSRob Herring }; 20266ed144fSRob Herring 20366ed144fSRob Herring - | 20466ed144fSRob Herring // GICv2m extension for MSI/MSI-x support 20566ed144fSRob Herring interrupt-controller@e1101000 { 20666ed144fSRob Herring compatible = "arm,gic-400"; 20766ed144fSRob Herring #interrupt-cells = <3>; 2088d665693SRob Herring #address-cells = <1>; 2098d665693SRob Herring #size-cells = <1>; 21066ed144fSRob Herring interrupt-controller; 21166ed144fSRob Herring interrupts = <1 8 0xf04>; 2128d665693SRob Herring ranges = <0 0xe1100000 0x100000>; 2138d665693SRob Herring reg = <0xe1110000 0x01000>, 2148d665693SRob Herring <0xe112f000 0x02000>, 2158d665693SRob Herring <0xe1140000 0x10000>, 2168d665693SRob Herring <0xe1160000 0x10000>; 21766ed144fSRob Herring 2188d665693SRob Herring v2m0: v2m@80000 { 21966ed144fSRob Herring compatible = "arm,gic-v2m-frame"; 22066ed144fSRob Herring msi-controller; 2218d665693SRob Herring reg = <0x80000 0x1000>; 22266ed144fSRob Herring }; 22366ed144fSRob Herring 22466ed144fSRob Herring //... 22566ed144fSRob Herring 2268d665693SRob Herring v2mN: v2m@90000 { 22766ed144fSRob Herring compatible = "arm,gic-v2m-frame"; 22866ed144fSRob Herring msi-controller; 2298d665693SRob Herring reg = <0x90000 0x1000>; 23066ed144fSRob Herring }; 23166ed144fSRob Herring }; 23266ed144fSRob Herring... 233