1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/interrupt-controller/apple,aic2.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Apple Interrupt Controller 2 and 3 8 9maintainers: 10 - Janne Grunau <j@jannau.net> 11 12description: | 13 The Apple Interrupt Controller 2 is a simple interrupt controller present on 14 Apple ARM SoC platforms starting with t600x (M1 Pro and Max). 15 16 It provides the following features: 17 18 - Level-triggered hardware IRQs wired to SoC blocks 19 - Single mask bit per IRQ 20 - Automatic masking on event delivery (auto-ack) 21 - Software triggering (ORed with hw line) 22 - Automatic prioritization (single event/ack register per CPU, lower IRQs = 23 higher priority) 24 - Automatic masking on ack 25 - Support for multiple dies 26 27 This device also represents the FIQ interrupt sources on platforms using AIC, 28 which do not go through a discrete interrupt controller. It also handles 29 FIQ-based Fast IPIs. 30 31 The Apple Interrupt Controller 3 is in its base functionality very similar to 32 the Apple Interrupt Controller 2 and uses the same device tree bindings. It is 33 found on Apple ARM SoCs platforms starting with t8122 (M3). 34 35properties: 36 compatible: 37 oneOf: 38 - items: 39 - enum: 40 - apple,t6000-aic 41 - apple,t6020-aic 42 - apple,t8112-aic 43 - const: apple,aic2 44 - items: 45 - enum: 46 - apple,t6030-aic3 47 - apple,t6031-aic3 48 - const: apple,t8122-aic3 49 - const: apple,t8122-aic3 50 51 interrupt-controller: true 52 53 '#interrupt-cells': 54 minimum: 3 55 maximum: 4 56 description: | 57 The 1st cell contains the interrupt type: 58 - 0: Hardware IRQ 59 - 1: FIQ 60 61 The 2nd cell contains the die ID (only present on apple,t6000-aic). 62 63 The next cell contains the interrupt number. 64 - HW IRQs: interrupt number 65 - FIQs: 66 - 0: physical HV timer 67 - 1: virtual HV timer 68 - 2: physical guest timer 69 - 3: virtual guest timer 70 71 The last cell contains the interrupt flags. This is normally 72 IRQ_TYPE_LEVEL_HIGH (4). 73 74 reg: 75 items: 76 - description: Address and size of the main AIC2 registers. 77 - description: Address and size of the AIC2 Event register. 78 79 reg-names: 80 items: 81 - const: core 82 - const: event 83 84 power-domains: 85 maxItems: 1 86 87 affinities: 88 type: object 89 additionalProperties: false 90 description: 91 FIQ affinity can be expressed as a single "affinities" node, 92 containing a set of sub-nodes, one per FIQ with a non-default 93 affinity. 94 patternProperties: 95 "^.+-affinity$": 96 type: object 97 additionalProperties: false 98 properties: 99 apple,fiq-index: 100 description: 101 The interrupt number specified as a FIQ, and for which 102 the affinity is not the default. 103 $ref: /schemas/types.yaml#/definitions/uint32 104 maximum: 5 105 106 cpus: 107 $ref: /schemas/types.yaml#/definitions/phandle-array 108 description: 109 Should be a list of phandles to CPU nodes (as described in 110 Documentation/devicetree/bindings/arm/cpus.yaml). 111 112 required: 113 - apple,fiq-index 114 - cpus 115 116required: 117 - compatible 118 - '#interrupt-cells' 119 - interrupt-controller 120 - reg 121 - reg-names 122 123additionalProperties: false 124 125allOf: 126 - $ref: /schemas/interrupt-controller.yaml# 127 - if: 128 properties: 129 compatible: 130 contains: 131 enum: 132 - apple,t6000-aic 133 - apple,t6020-aic 134 - apple,t6031-aic3 135 then: 136 properties: 137 '#interrupt-cells': 138 const: 4 139 else: 140 properties: 141 '#interrupt-cells': 142 const: 3 143 144examples: 145 - | 146 soc { 147 #address-cells = <2>; 148 #size-cells = <2>; 149 150 aic: interrupt-controller@28e100000 { 151 compatible = "apple,t6000-aic", "apple,aic2"; 152 #interrupt-cells = <4>; 153 interrupt-controller; 154 reg = <0x2 0x8e100000 0x0 0xc000>, 155 <0x2 0x8e10c000 0x0 0x4>; 156 reg-names = "core", "event"; 157 }; 158 }; 159