1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/interrupt-controller/apple,aic2.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Apple Interrupt Controller 2 and 3 8 9maintainers: 10 - Janne Grunau <j@jannau.net> 11 12description: | 13 The Apple Interrupt Controller 2 is a simple interrupt controller present on 14 Apple ARM SoC platforms starting with t600x (M1 Pro and Max). 15 16 It provides the following features: 17 18 - Level-triggered hardware IRQs wired to SoC blocks 19 - Single mask bit per IRQ 20 - Automatic masking on event delivery (auto-ack) 21 - Software triggering (ORed with hw line) 22 - Automatic prioritization (single event/ack register per CPU, lower IRQs = 23 higher priority) 24 - Automatic masking on ack 25 - Support for multiple dies 26 27 This device also represents the FIQ interrupt sources on platforms using AIC, 28 which do not go through a discrete interrupt controller. It also handles 29 FIQ-based Fast IPIs. 30 31 The Apple Interrupt Controller 3 is in its base functionality very similar to 32 the Apple Interrupt Controller 2 and uses the same device tree bindings. It is 33 found on Apple ARM SoCs platforms starting with t8122 (M3). 34 35properties: 36 compatible: 37 oneOf: 38 - items: 39 - enum: 40 - apple,t6000-aic 41 - apple,t6020-aic 42 - apple,t8112-aic 43 - const: apple,aic2 44 - items: 45 - enum: 46 - apple,t6030-aic3 47 - const: apple,t8122-aic3 48 - const: apple,t8122-aic3 49 50 interrupt-controller: true 51 52 '#interrupt-cells': 53 minimum: 3 54 maximum: 4 55 description: | 56 The 1st cell contains the interrupt type: 57 - 0: Hardware IRQ 58 - 1: FIQ 59 60 The 2nd cell contains the die ID (only present on apple,t6000-aic). 61 62 The next cell contains the interrupt number. 63 - HW IRQs: interrupt number 64 - FIQs: 65 - 0: physical HV timer 66 - 1: virtual HV timer 67 - 2: physical guest timer 68 - 3: virtual guest timer 69 70 The last cell contains the interrupt flags. This is normally 71 IRQ_TYPE_LEVEL_HIGH (4). 72 73 reg: 74 items: 75 - description: Address and size of the main AIC2 registers. 76 - description: Address and size of the AIC2 Event register. 77 78 reg-names: 79 items: 80 - const: core 81 - const: event 82 83 power-domains: 84 maxItems: 1 85 86 affinities: 87 type: object 88 additionalProperties: false 89 description: 90 FIQ affinity can be expressed as a single "affinities" node, 91 containing a set of sub-nodes, one per FIQ with a non-default 92 affinity. 93 patternProperties: 94 "^.+-affinity$": 95 type: object 96 additionalProperties: false 97 properties: 98 apple,fiq-index: 99 description: 100 The interrupt number specified as a FIQ, and for which 101 the affinity is not the default. 102 $ref: /schemas/types.yaml#/definitions/uint32 103 maximum: 5 104 105 cpus: 106 $ref: /schemas/types.yaml#/definitions/phandle-array 107 description: 108 Should be a list of phandles to CPU nodes (as described in 109 Documentation/devicetree/bindings/arm/cpus.yaml). 110 111 required: 112 - apple,fiq-index 113 - cpus 114 115required: 116 - compatible 117 - '#interrupt-cells' 118 - interrupt-controller 119 - reg 120 - reg-names 121 122additionalProperties: false 123 124allOf: 125 - $ref: /schemas/interrupt-controller.yaml# 126 - if: 127 properties: 128 compatible: 129 contains: 130 enum: 131 - apple,t8112-aic 132 - apple,t8122-aic3 133 then: 134 properties: 135 '#interrupt-cells': 136 const: 3 137 else: 138 properties: 139 '#interrupt-cells': 140 const: 4 141 142examples: 143 - | 144 soc { 145 #address-cells = <2>; 146 #size-cells = <2>; 147 148 aic: interrupt-controller@28e100000 { 149 compatible = "apple,t6000-aic", "apple,aic2"; 150 #interrupt-cells = <4>; 151 interrupt-controller; 152 reg = <0x2 0x8e100000 0x0 0xc000>, 153 <0x2 0x8e10c000 0x0 0x4>; 154 reg-names = "core", "event"; 155 }; 156 }; 157