1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/interrupt-controller/apple,aic2.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Apple Interrupt Controller 2 and 3 8 9maintainers: 10 - Janne Grunau <j@jannau.net> 11 12description: | 13 The Apple Interrupt Controller 2 is a simple interrupt controller present on 14 Apple ARM SoC platforms starting with t600x (M1 Pro and Max). 15 16 It provides the following features: 17 18 - Level-triggered hardware IRQs wired to SoC blocks 19 - Single mask bit per IRQ 20 - Automatic masking on event delivery (auto-ack) 21 - Software triggering (ORed with hw line) 22 - Automatic prioritization (single event/ack register per CPU, lower IRQs = 23 higher priority) 24 - Automatic masking on ack 25 - Support for multiple dies 26 27 This device also represents the FIQ interrupt sources on platforms using AIC, 28 which do not go through a discrete interrupt controller. It also handles 29 FIQ-based Fast IPIs. 30 31 The Apple Interrupt Controller 3 is in its base functionality very similar to 32 the Apple Interrupt Controller 2 and uses the same device tree bindings. It is 33 found on Apple ARM SoCs platforms starting with t8122 (M3). 34 35properties: 36 compatible: 37 oneOf: 38 - items: 39 - enum: 40 - apple,t6000-aic 41 - apple,t6020-aic 42 - apple,t8112-aic 43 - const: apple,aic2 44 - items: 45 - enum: 46 - apple,t6030-aic3 47 - apple,t6031-aic3 48 - apple,t8132-aic3 49 - apple,t8140-aic3 50 - const: apple,t8122-aic3 51 - const: apple,t8122-aic3 52 53 interrupt-controller: true 54 55 '#interrupt-cells': 56 minimum: 3 57 maximum: 4 58 description: | 59 The 1st cell contains the interrupt type: 60 - 0: Hardware IRQ 61 - 1: FIQ 62 63 The 2nd cell contains the die ID (only present on apple,t6000-aic). 64 65 The next cell contains the interrupt number. 66 - HW IRQs: interrupt number 67 - FIQs: 68 - 0: physical HV timer 69 - 1: virtual HV timer 70 - 2: physical guest timer 71 - 3: virtual guest timer 72 73 The last cell contains the interrupt flags. This is normally 74 IRQ_TYPE_LEVEL_HIGH (4). 75 76 reg: 77 items: 78 - description: Address and size of the main AIC2 registers. 79 - description: Address and size of the AIC2 Event register. 80 81 reg-names: 82 items: 83 - const: core 84 - const: event 85 86 power-domains: 87 maxItems: 1 88 89 affinities: 90 type: object 91 additionalProperties: false 92 description: 93 FIQ affinity can be expressed as a single "affinities" node, 94 containing a set of sub-nodes, one per FIQ with a non-default 95 affinity. 96 patternProperties: 97 "^.+-affinity$": 98 type: object 99 additionalProperties: false 100 properties: 101 apple,fiq-index: 102 description: 103 The interrupt number specified as a FIQ, and for which 104 the affinity is not the default. 105 $ref: /schemas/types.yaml#/definitions/uint32 106 maximum: 5 107 108 cpus: 109 $ref: /schemas/types.yaml#/definitions/phandle-array 110 description: 111 Should be a list of phandles to CPU nodes (as described in 112 Documentation/devicetree/bindings/arm/cpus.yaml). 113 114 required: 115 - apple,fiq-index 116 - cpus 117 118required: 119 - compatible 120 - '#interrupt-cells' 121 - interrupt-controller 122 - reg 123 - reg-names 124 125additionalProperties: false 126 127allOf: 128 - $ref: /schemas/interrupt-controller.yaml# 129 - if: 130 properties: 131 compatible: 132 contains: 133 enum: 134 - apple,t6000-aic 135 - apple,t6020-aic 136 - apple,t6031-aic3 137 then: 138 properties: 139 '#interrupt-cells': 140 const: 4 141 else: 142 properties: 143 '#interrupt-cells': 144 const: 3 145 146examples: 147 - | 148 soc { 149 #address-cells = <2>; 150 #size-cells = <2>; 151 152 aic: interrupt-controller@28e100000 { 153 compatible = "apple,t6000-aic", "apple,aic2"; 154 #interrupt-cells = <4>; 155 interrupt-controller; 156 reg = <0x2 0x8e100000 0x0 0xc000>, 157 <0x2 0x8e10c000 0x0 0x4>; 158 reg-names = "core", "event"; 159 }; 160 }; 161