xref: /linux/Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml (revision 9fd2da71c301184d98fe37674ca8d017d1ce6600) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/interrupt-controller/andestech,plicsw.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Andes machine-level software interrupt controller
8
9description:
10  In the Andes platform such as QiLai SoC, the PLIC module is instantiated a
11  second time with all interrupt sources tied to zero as the software interrupt
12  controller (PLIC_SW). PLIC_SW directly connects to the machine-mode
13  inter-processor interrupt lines of CPUs, so RISC-V per-CPU local interrupt
14  controller is the parent interrupt controller for PLIC_SW. PLIC_SW can
15  generate machine-mode inter-processor interrupts through programming its
16  registers.
17
18maintainers:
19  - Ben Zong-You Xie <ben717@andestech.com>
20
21properties:
22  compatible:
23    items:
24      - enum:
25          - andestech,qilai-plicsw
26      - const: andestech,plicsw
27
28  reg:
29    maxItems: 1
30
31  interrupts-extended:
32    minItems: 1
33    maxItems: 15872
34    description:
35      Specifies which harts are connected to the PLIC_SW. Each item must points
36      to a riscv,cpu-intc node, which has a riscv cpu node as parent.
37
38additionalProperties: false
39
40required:
41  - compatible
42  - reg
43  - interrupts-extended
44
45examples:
46  - |
47    interrupt-controller@400000 {
48      compatible = "andestech,qilai-plicsw", "andestech,plicsw";
49      reg = <0x400000 0x400000>;
50      interrupts-extended = <&cpu0intc 3>,
51                            <&cpu1intc 3>,
52                            <&cpu2intc 3>,
53                            <&cpu3intc 3>;
54    };
55