1*a1369029SAntoine TenartAlpine MSIX controller 2*a1369029SAntoine Tenart 3*a1369029SAntoine TenartSee arm,gic-v3.txt for SPI and MSI definitions. 4*a1369029SAntoine Tenart 5*a1369029SAntoine TenartRequired properties: 6*a1369029SAntoine Tenart 7*a1369029SAntoine Tenart- compatible: should be "al,alpine-msix" 8*a1369029SAntoine Tenart- reg: physical base address and size of the registers 9*a1369029SAntoine Tenart- interrupt-controller: identifies the node as an interrupt controller 10*a1369029SAntoine Tenart- msi-controller: identifies the node as an PCI Message Signaled Interrupt 11*a1369029SAntoine Tenart controller 12*a1369029SAntoine Tenart- al,msi-base-spi: SPI base of the MSI frame 13*a1369029SAntoine Tenart- al,msi-num-spis: number of SPIs assigned to the MSI frame, relative to SPI0 14*a1369029SAntoine Tenart 15*a1369029SAntoine TenartExample: 16*a1369029SAntoine Tenart 17*a1369029SAntoine Tenartmsix: msix { 18*a1369029SAntoine Tenart compatible = "al,alpine-msix"; 19*a1369029SAntoine Tenart reg = <0x0 0xfbe00000 0x0 0x100000>; 20*a1369029SAntoine Tenart interrupt-parent = <&gic>; 21*a1369029SAntoine Tenart interrupt-controller; 22*a1369029SAntoine Tenart msi-controller; 23*a1369029SAntoine Tenart al,msi-base-spi = <160>; 24*a1369029SAntoine Tenart al,msi-num-spis = <160>; 25*a1369029SAntoine Tenart}; 26