xref: /linux/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml (revision db4a3f0fbedb0398f77b9047e8b8bb2b49f355bb) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/interconnect/qcom,osm-l3.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Operating State Manager (OSM) L3 Interconnect Provider
8
9maintainers:
10  - Sibi Sankar <quic_sibis@quicinc.com>
11
12description:
13  L3 cache bandwidth requirements on Qualcomm SoCs is serviced by the OSM.
14  The OSM L3 interconnect provider aggregates the L3 bandwidth requests
15  from CPU/GPU and relays it to the OSM.
16
17properties:
18  compatible:
19    oneOf:
20      - items:
21          - enum:
22              - qcom,sc7180-osm-l3
23              - qcom,sc8180x-osm-l3
24              - qcom,sdm670-osm-l3
25              - qcom,sdm845-osm-l3
26              - qcom,sm6350-osm-l3
27              - qcom,sm8150-osm-l3
28          - const: qcom,osm-l3
29      - items:
30          - enum:
31              - qcom,sa8775p-epss-l3
32              - qcom,sc7280-epss-l3
33              - qcom,sc8280xp-epss-l3
34              - qcom,sm6375-cpucp-l3
35              - qcom,sm8250-epss-l3
36              - qcom,sm8350-epss-l3
37              - qcom,sm8650-epss-l3
38          - const: qcom,epss-l3
39      - items:
40          - enum:
41              - qcom,qcs8300-epss-l3
42          - const: qcom,sa8775p-epss-l3
43          - const: qcom,epss-l3
44      - items:
45          - enum:
46              - qcom,qcs615-osm-l3
47          - const: qcom,sm8150-osm-l3
48          - const: qcom,osm-l3
49
50  reg:
51    maxItems: 1
52
53  clocks:
54    items:
55      - description: xo clock
56      - description: alternate clock
57
58  clock-names:
59    items:
60      - const: xo
61      - const: alternate
62
63  '#interconnect-cells':
64    const: 1
65
66required:
67  - compatible
68  - reg
69  - clocks
70  - clock-names
71  - '#interconnect-cells'
72
73additionalProperties: false
74
75examples:
76  - |
77
78    #define GPLL0               165
79    #define RPMH_CXO_CLK        0
80
81    osm_l3: interconnect@17d41000 {
82      compatible = "qcom,sdm845-osm-l3", "qcom,osm-l3";
83      reg = <0x17d41000 0x1400>;
84
85      clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
86      clock-names = "xo", "alternate";
87
88      #interconnect-cells = <1>;
89    };
90