xref: /linux/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml (revision 8a922b7728a93d837954315c98b84f6b78de0c4f) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/interconnect/qcom,osm-l3.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Operating State Manager (OSM) L3 Interconnect Provider
8
9maintainers:
10  - Sibi Sankar <quic_sibis@quicinc.com>
11
12description:
13  L3 cache bandwidth requirements on Qualcomm SoCs is serviced by the OSM.
14  The OSM L3 interconnect provider aggregates the L3 bandwidth requests
15  from CPU/GPU and relays it to the OSM.
16
17properties:
18  compatible:
19    oneOf:
20      - items:
21          - enum:
22              - qcom,sc7180-osm-l3
23              - qcom,sc8180x-osm-l3
24              - qcom,sdm845-osm-l3
25              - qcom,sm6350-osm-l3
26              - qcom,sm8150-osm-l3
27          - const: qcom,osm-l3
28      - items:
29          - enum:
30              - qcom,sc7280-epss-l3
31              - qcom,sc8280xp-epss-l3
32              - qcom,sm8250-epss-l3
33              - qcom,sm8350-epss-l3
34          - const: qcom,epss-l3
35
36  reg:
37    maxItems: 1
38
39  clocks:
40    items:
41      - description: xo clock
42      - description: alternate clock
43
44  clock-names:
45    items:
46      - const: xo
47      - const: alternate
48
49  '#interconnect-cells':
50    const: 1
51
52required:
53  - compatible
54  - reg
55  - clocks
56  - clock-names
57  - '#interconnect-cells'
58
59additionalProperties: false
60
61examples:
62  - |
63
64    #define GPLL0               165
65    #define RPMH_CXO_CLK        0
66
67    osm_l3: interconnect@17d41000 {
68      compatible = "qcom,sdm845-osm-l3", "qcom,osm-l3";
69      reg = <0x17d41000 0x1400>;
70
71      clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
72      clock-names = "xo", "alternate";
73
74      #interconnect-cells = <1>;
75    };
76