1*0f29e33fSLuca Weiss# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*0f29e33fSLuca Weiss%YAML 1.2 3*0f29e33fSLuca Weiss--- 4*0f29e33fSLuca Weiss$id: http://devicetree.org/schemas/interconnect/qcom,milos-rpmh.yaml# 5*0f29e33fSLuca Weiss$schema: http://devicetree.org/meta-schemas/core.yaml# 6*0f29e33fSLuca Weiss 7*0f29e33fSLuca Weisstitle: Qualcomm RPMh Network-On-Chip Interconnect on Milos SoC 8*0f29e33fSLuca Weiss 9*0f29e33fSLuca Weissmaintainers: 10*0f29e33fSLuca Weiss - Luca Weiss <luca.weiss@fairphone.com> 11*0f29e33fSLuca Weiss 12*0f29e33fSLuca Weissdescription: | 13*0f29e33fSLuca Weiss RPMh interconnect providers support system bandwidth requirements through 14*0f29e33fSLuca Weiss RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is 15*0f29e33fSLuca Weiss able to communicate with the BCM through the Resource State Coordinator (RSC) 16*0f29e33fSLuca Weiss associated with each execution environment. Provider nodes must point to at 17*0f29e33fSLuca Weiss least one RPMh device child node pertaining to their RSC and each provider 18*0f29e33fSLuca Weiss can map to multiple RPMh resources. 19*0f29e33fSLuca Weiss 20*0f29e33fSLuca Weiss See also: include/dt-bindings/interconnect/qcom,milos-rpmh.h 21*0f29e33fSLuca Weiss 22*0f29e33fSLuca Weissproperties: 23*0f29e33fSLuca Weiss compatible: 24*0f29e33fSLuca Weiss enum: 25*0f29e33fSLuca Weiss - qcom,milos-aggre1-noc 26*0f29e33fSLuca Weiss - qcom,milos-aggre2-noc 27*0f29e33fSLuca Weiss - qcom,milos-clk-virt 28*0f29e33fSLuca Weiss - qcom,milos-cnoc-cfg 29*0f29e33fSLuca Weiss - qcom,milos-cnoc-main 30*0f29e33fSLuca Weiss - qcom,milos-gem-noc 31*0f29e33fSLuca Weiss - qcom,milos-lpass-ag-noc 32*0f29e33fSLuca Weiss - qcom,milos-mc-virt 33*0f29e33fSLuca Weiss - qcom,milos-mmss-noc 34*0f29e33fSLuca Weiss - qcom,milos-nsp-noc 35*0f29e33fSLuca Weiss - qcom,milos-pcie-anoc 36*0f29e33fSLuca Weiss - qcom,milos-system-noc 37*0f29e33fSLuca Weiss 38*0f29e33fSLuca Weiss reg: 39*0f29e33fSLuca Weiss maxItems: 1 40*0f29e33fSLuca Weiss 41*0f29e33fSLuca Weiss clocks: 42*0f29e33fSLuca Weiss minItems: 1 43*0f29e33fSLuca Weiss maxItems: 2 44*0f29e33fSLuca Weiss 45*0f29e33fSLuca Weissrequired: 46*0f29e33fSLuca Weiss - compatible 47*0f29e33fSLuca Weiss 48*0f29e33fSLuca WeissallOf: 49*0f29e33fSLuca Weiss - $ref: qcom,rpmh-common.yaml# 50*0f29e33fSLuca Weiss - if: 51*0f29e33fSLuca Weiss properties: 52*0f29e33fSLuca Weiss compatible: 53*0f29e33fSLuca Weiss contains: 54*0f29e33fSLuca Weiss enum: 55*0f29e33fSLuca Weiss - qcom,milos-clk-virt 56*0f29e33fSLuca Weiss - qcom,milos-mc-virt 57*0f29e33fSLuca Weiss then: 58*0f29e33fSLuca Weiss properties: 59*0f29e33fSLuca Weiss reg: false 60*0f29e33fSLuca Weiss else: 61*0f29e33fSLuca Weiss required: 62*0f29e33fSLuca Weiss - reg 63*0f29e33fSLuca Weiss 64*0f29e33fSLuca Weiss - if: 65*0f29e33fSLuca Weiss properties: 66*0f29e33fSLuca Weiss compatible: 67*0f29e33fSLuca Weiss contains: 68*0f29e33fSLuca Weiss enum: 69*0f29e33fSLuca Weiss - qcom,milos-pcie-anoc 70*0f29e33fSLuca Weiss then: 71*0f29e33fSLuca Weiss properties: 72*0f29e33fSLuca Weiss clocks: 73*0f29e33fSLuca Weiss items: 74*0f29e33fSLuca Weiss - description: aggre-NOC PCIe AXI clock 75*0f29e33fSLuca Weiss - description: cfg-NOC PCIe a-NOC AHB clock 76*0f29e33fSLuca Weiss 77*0f29e33fSLuca Weiss - if: 78*0f29e33fSLuca Weiss properties: 79*0f29e33fSLuca Weiss compatible: 80*0f29e33fSLuca Weiss contains: 81*0f29e33fSLuca Weiss enum: 82*0f29e33fSLuca Weiss - qcom,milos-aggre1-noc 83*0f29e33fSLuca Weiss then: 84*0f29e33fSLuca Weiss properties: 85*0f29e33fSLuca Weiss clocks: 86*0f29e33fSLuca Weiss items: 87*0f29e33fSLuca Weiss - description: aggre USB3 PRIM AXI clock 88*0f29e33fSLuca Weiss - description: aggre UFS PHY AXI clock 89*0f29e33fSLuca Weiss 90*0f29e33fSLuca Weiss - if: 91*0f29e33fSLuca Weiss properties: 92*0f29e33fSLuca Weiss compatible: 93*0f29e33fSLuca Weiss contains: 94*0f29e33fSLuca Weiss enum: 95*0f29e33fSLuca Weiss - qcom,milos-aggre2-noc 96*0f29e33fSLuca Weiss then: 97*0f29e33fSLuca Weiss properties: 98*0f29e33fSLuca Weiss clocks: 99*0f29e33fSLuca Weiss items: 100*0f29e33fSLuca Weiss - description: RPMH CC IPA clock 101*0f29e33fSLuca Weiss 102*0f29e33fSLuca Weiss - if: 103*0f29e33fSLuca Weiss properties: 104*0f29e33fSLuca Weiss compatible: 105*0f29e33fSLuca Weiss contains: 106*0f29e33fSLuca Weiss enum: 107*0f29e33fSLuca Weiss - qcom,milos-aggre1-noc 108*0f29e33fSLuca Weiss - qcom,milos-aggre2-noc 109*0f29e33fSLuca Weiss - qcom,milos-pcie-anoc 110*0f29e33fSLuca Weiss then: 111*0f29e33fSLuca Weiss required: 112*0f29e33fSLuca Weiss - clocks 113*0f29e33fSLuca Weiss else: 114*0f29e33fSLuca Weiss properties: 115*0f29e33fSLuca Weiss clocks: false 116*0f29e33fSLuca Weiss 117*0f29e33fSLuca WeissunevaluatedProperties: false 118*0f29e33fSLuca Weiss 119*0f29e33fSLuca Weissexamples: 120*0f29e33fSLuca Weiss - | 121*0f29e33fSLuca Weiss #include <dt-bindings/clock/qcom,milos-gcc.h> 122*0f29e33fSLuca Weiss 123*0f29e33fSLuca Weiss interconnect-0 { 124*0f29e33fSLuca Weiss compatible = "qcom,milos-clk-virt"; 125*0f29e33fSLuca Weiss #interconnect-cells = <2>; 126*0f29e33fSLuca Weiss qcom,bcm-voters = <&apps_bcm_voter>; 127*0f29e33fSLuca Weiss }; 128*0f29e33fSLuca Weiss 129*0f29e33fSLuca Weiss interconnect@16e0000 { 130*0f29e33fSLuca Weiss compatible = "qcom,milos-aggre1-noc"; 131*0f29e33fSLuca Weiss reg = <0x016e0000 0x16400>; 132*0f29e33fSLuca Weiss #interconnect-cells = <2>; 133*0f29e33fSLuca Weiss clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 134*0f29e33fSLuca Weiss <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; 135*0f29e33fSLuca Weiss qcom,bcm-voters = <&apps_bcm_voter>; 136*0f29e33fSLuca Weiss }; 137