xref: /linux/Documentation/devicetree/bindings/interconnect/qcom,glymur-rpmh.yaml (revision cb4eb6771c0f8fd1c52a8f6fdec7762fb087380a)

# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interconnect/qcom,glymur-rpmh.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm RPMh Network-On-Chip Interconnect on Glymur and Mahua SoCs

maintainers:
  - Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>

description: |
  RPMh interconnect providers support system bandwidth requirements through
  RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
  able to communicate with the BCM through the Resource State Coordinator (RSC)
  associated with each execution environment. Provider nodes must point to at
  least one RPMh device child node pertaining to their RSC and each provider
  can map to multiple RPMh resources.

  See also: include/dt-bindings/interconnect/qcom,glymur-rpmh.h

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - qcom,mahua-aggre1-noc
          - const: qcom,glymur-aggre1-noc
      - items:
          - enum:
              - qcom,mahua-aggre2-noc
          - const: qcom,glymur-aggre2-noc
      - items:
          - enum:
              - qcom,mahua-aggre3-noc
          - const: qcom,glymur-aggre3-noc
      - items:
          - enum:
              - qcom,mahua-aggre4-noc
          - const: qcom,glymur-aggre4-noc
      - items:
          - enum:
              - qcom,mahua-clk-virt
          - const: qcom,glymur-clk-virt
      - items:
          - enum:
              - qcom,mahua-cnoc-main
          - const: qcom,glymur-cnoc-main
      - items:
          - enum:
              - qcom,mahua-lpass-ag-noc
          - const: qcom,glymur-lpass-ag-noc
      - items:
          - enum:
              - qcom,mahua-lpass-lpiaon-noc
          - const: qcom,glymur-lpass-lpiaon-noc
      - items:
          - enum:
              - qcom,mahua-lpass-lpicx-noc
          - const: qcom,glymur-lpass-lpicx-noc
      - items:
          - enum:
              - qcom,mahua-mmss-noc
          - const: qcom,glymur-mmss-noc
      - items:
          - enum:
              - qcom,mahua-nsinoc
          - const: qcom,glymur-nsinoc
      - items:
          - enum:
              - qcom,mahua-nsp-noc
          - const: qcom,glymur-nsp-noc
      - items:
          - enum:
              - qcom,mahua-oobm-ss-noc
          - const: qcom,glymur-oobm-ss-noc
      - items:
          - enum:
              - qcom,mahua-pcie-east-anoc
          - const: qcom,glymur-pcie-east-anoc
      - items:
          - enum:
              - qcom,mahua-pcie-east-slv-noc
          - const: qcom,glymur-pcie-east-slv-noc
      - items:
          - enum:
              - qcom,mahua-system-noc
          - const: qcom,glymur-system-noc
      - enum:
          - qcom,glymur-aggre1-noc
          - qcom,glymur-aggre2-noc
          - qcom,glymur-aggre3-noc
          - qcom,glymur-aggre4-noc
          - qcom,glymur-clk-virt
          - qcom,glymur-cnoc-cfg
          - qcom,glymur-cnoc-main
          - qcom,glymur-hscnoc
          - qcom,glymur-lpass-ag-noc
          - qcom,glymur-lpass-lpiaon-noc
          - qcom,glymur-lpass-lpicx-noc
          - qcom,glymur-mc-virt
          - qcom,glymur-mmss-noc
          - qcom,glymur-nsinoc
          - qcom,glymur-nsp-noc
          - qcom,glymur-oobm-ss-noc
          - qcom,glymur-pcie-east-anoc
          - qcom,glymur-pcie-east-slv-noc
          - qcom,glymur-pcie-west-anoc
          - qcom,glymur-pcie-west-slv-noc
          - qcom,glymur-system-noc
          - qcom,mahua-cnoc-cfg
          - qcom,mahua-hscnoc
          - qcom,mahua-mc-virt
          - qcom,mahua-pcie-west-anoc
          - qcom,mahua-pcie-west-slv-noc

  reg:
    maxItems: 1

  clocks:
    minItems: 1
    maxItems: 4

required:
  - compatible

allOf:
  - $ref: qcom,rpmh-common.yaml#
  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,glymur-clk-virt
              - qcom,glymur-mc-virt
              - qcom,mahua-mc-virt
    then:
      properties:
        reg: false
    else:
      required:
        - reg

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,glymur-pcie-west-anoc
    then:
      properties:
        clocks:
          items:
            - description: aggre PCIE_3A WEST AXI clock
            - description: aggre PCIE_3B WEST AXI clock
            - description: aggre PCIE_4 WEST AXI clock
            - description: aggre PCIE_6 WEST AXI clock

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,mahua-pcie-west-anoc
    then:
      properties:
        clocks:
          items:
            - description: aggre PCIE_3B WEST AXI clock
            - description: aggre PCIE_4 WEST AXI clock
            - description: aggre PCIE_6 WEST AXI clock

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,glymur-pcie-east-anoc
    then:
      properties:
        clocks:
          items:
            - description: aggre PCIE_5 EAST AXI clock

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,glymur-aggre2-noc
    then:
      properties:
        clocks:
          items:
            - description: aggre USB3 TERT AXI clock
            - description: aggre USB4_2 AXI clock
            - description: aggre UFS PHY AXI clock

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,glymur-aggre4-noc
    then:
      properties:
        clocks:
          items:
            - description: aggre USB3 PRIM AXI clock
            - description: aggre USB3 SEC AXI clock
            - description: aggre USB4_0 AXI clock
            - description: aggre USB4_1 AXI clock

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,glymur-aggre2-noc
              - qcom,glymur-aggre4-noc
              - qcom,glymur-pcie-east-anoc
              - qcom,glymur-pcie-west-anoc
              - qcom,mahua-pcie-west-anoc
    then:
      required:
        - clocks
    else:
      properties:
        clocks: false

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,glymur-gcc.h>
    clk_virt: interconnect-0 {
      compatible = "qcom,glymur-clk-virt";
      #interconnect-cells = <2>;
      qcom,bcm-voters = <&apps_bcm_voter>;
    };

    aggre1_noc: interconnect@16e0000 {
      compatible = "qcom,glymur-aggre1-noc";
      reg = <0x016e0000 0x14400>;
      #interconnect-cells = <2>;
      qcom,bcm-voters = <&apps_bcm_voter>;
    };

    aggre4_noc: interconnect@1740000 {
      compatible = "qcom,glymur-aggre4-noc";
      reg = <0x01740000 0x14400>;
      #interconnect-cells = <2>;
      qcom,bcm-voters = <&apps_bcm_voter>;
      clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
               <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
               <&gcc GCC_AGGRE_USB4_0_AXI_CLK>,
               <&gcc GCC_AGGRE_USB4_1_AXI_CLK>;
    };