1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/iio/imu/adi,adis16480.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Analog Devices ADIS16480 and similar IMUs 8 9maintainers: 10 - Marcelo Schmitt <marcelo.schmitt@analog.com> 11 - Nuno Sá <nuno.sa@analog.com> 12 13properties: 14 compatible: 15 oneOf: 16 - enum: 17 - adi,adis16375 18 - adi,adis16480 19 - adi,adis16485 20 - adi,adis16486 21 - adi,adis16488 22 - adi,adis16489 23 - adi,adis16490 24 - adi,adis16495-1 25 - adi,adis16495-2 26 - adi,adis16495-3 27 - adi,adis16497-1 28 - adi,adis16497-2 29 - adi,adis16497-3 30 - adi,adis16545-1 31 - adi,adis16545-2 32 - adi,adis16545-3 33 - adi,adis16547-1 34 - adi,adis16547-2 35 - adi,adis16547-3 36 - items: 37 - const: adi,adis16487 38 - const: adi,adis16485 39 40 reg: 41 maxItems: 1 42 43 interrupts: 44 minItems: 1 45 maxItems: 2 46 description: | 47 Accepted interrupt types are: 48 * IRQ_TYPE_EDGE_RISING 49 * IRQ_TYPE_EDGE_FALLING 50 51 interrupt-names: 52 minItems: 1 53 maxItems: 2 54 description: 55 Default if not supplied is DIO1. 56 items: 57 enum: 58 - DIO1 59 - DIO2 60 - DIO3 61 - DIO4 62 63 spi-cpha: true 64 spi-cpol: true 65 66 reset-gpios: 67 maxItems: 1 68 description: Connected to RESET pin which is active low. 69 70 clocks: 71 maxItems: 1 72 description: If not provided, then the internal clock is used. 73 74 clock-names: 75 description: | 76 sync: In sync mode, the internal clock is disabled and the frequency 77 of the external clock signal establishes therate of data 78 collection and processing. See Fig 14 and 15 in the datasheet. 79 The clock-frequency must be: 80 * 3000 to 4500 Hz for adis1649x devices. 81 * 700 to 2400 Hz for adis1648x devices. 82 pps: In Pulse Per Second (PPS) Mode, the rate of data collection and 83 production is equal to the product of the external clock 84 frequency and the scale factor in the SYNC_SCALE register, see 85 Table 154 in the datasheet. 86 The clock-frequency must be: 87 * 1 to 128 Hz for adis1649x devices. 88 * This mode is not supported by adis1648x devices. 89 enum: 90 - sync 91 - pps 92 93 adi,ext-clk-pin: 94 $ref: /schemas/types.yaml#/definitions/string 95 description: | 96 The DIOx line to be used as an external clock input. 97 Each DIOx pin supports only one function at a time (data ready line 98 selection or external clock input). When a single pin has two 99 two assignments, the enable bit for the lower priority function 100 automatically resets to zero (disabling the lower priority function). 101 Data ready has highest priority. 102 If not provided then DIO2 is assigned as default external clock 103 input pin. 104 enum: 105 - DIO1 106 - DIO2 107 - DIO3 108 - DIO4 109 110required: 111 - compatible 112 - reg 113 - interrupts 114 - spi-cpha 115 - spi-cpol 116 - spi-max-frequency 117 118allOf: 119 - $ref: /schemas/spi/spi-peripheral-props.yaml# 120 121unevaluatedProperties: false 122 123examples: 124 - | 125 #include <dt-bindings/interrupt-controller/irq.h> 126 spi { 127 #address-cells = <1>; 128 #size-cells = <0>; 129 130 imu@0 { 131 compatible = "adi,adis16495-1"; 132 reg = <0>; 133 spi-max-frequency = <3200000>; 134 spi-cpol; 135 spi-cpha; 136 interrupts = <25 IRQ_TYPE_EDGE_FALLING>; 137 interrupt-parent = <&gpio>; 138 interrupt-names = "DIO2"; 139 clocks = <&adis16495_sync>; 140 clock-names = "sync"; 141 adi,ext-clk-pin = "DIO1"; 142 }; 143 }; 144... 145