1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/iio/imu/adi,adis16480.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Analog Devices ADIS16480 and similar IMUs 8 9maintainers: 10 - Alexandru Tachici <alexandru.tachici@analog.com> 11 12properties: 13 compatible: 14 enum: 15 - adi,adis16375 16 - adi,adis16480 17 - adi,adis16485 18 - adi,adis16488 19 - adi,adis16490 20 - adi,adis16495-1 21 - adi,adis16495-2 22 - adi,adis16495-3 23 - adi,adis16497-1 24 - adi,adis16497-2 25 - adi,adis16497-3 26 - adi,adis16545-1 27 - adi,adis16545-2 28 - adi,adis16545-3 29 - adi,adis16547-1 30 - adi,adis16547-2 31 - adi,adis16547-3 32 33 reg: 34 maxItems: 1 35 36 interrupts: 37 minItems: 1 38 maxItems: 2 39 description: | 40 Accepted interrupt types are: 41 * IRQ_TYPE_EDGE_RISING 42 * IRQ_TYPE_EDGE_FALLING 43 44 interrupt-names: 45 minItems: 1 46 maxItems: 2 47 description: 48 Default if not supplied is DIO1. 49 items: 50 enum: 51 - DIO1 52 - DIO2 53 - DIO3 54 - DIO4 55 56 spi-cpha: true 57 spi-cpol: true 58 59 reset-gpios: 60 maxItems: 1 61 description: Connected to RESET pin which is active low. 62 63 clocks: 64 maxItems: 1 65 description: If not provided, then the internal clock is used. 66 67 clock-names: 68 description: | 69 sync: In sync mode, the internal clock is disabled and the frequency 70 of the external clock signal establishes therate of data 71 collection and processing. See Fig 14 and 15 in the datasheet. 72 The clock-frequency must be: 73 * 3000 to 4500 Hz for adis1649x devices. 74 * 700 to 2400 Hz for adis1648x devices. 75 pps: In Pulse Per Second (PPS) Mode, the rate of data collection and 76 production is equal to the product of the external clock 77 frequency and the scale factor in the SYNC_SCALE register, see 78 Table 154 in the datasheet. 79 The clock-frequency must be: 80 * 1 to 128 Hz for adis1649x devices. 81 * This mode is not supported by adis1648x devices. 82 enum: 83 - sync 84 - pps 85 86 adi,ext-clk-pin: 87 $ref: /schemas/types.yaml#/definitions/string 88 description: | 89 The DIOx line to be used as an external clock input. 90 Each DIOx pin supports only one function at a time (data ready line 91 selection or external clock input). When a single pin has two 92 two assignments, the enable bit for the lower priority function 93 automatically resets to zero (disabling the lower priority function). 94 Data ready has highest priority. 95 If not provided then DIO2 is assigned as default external clock 96 input pin. 97 enum: 98 - DIO1 99 - DIO2 100 - DIO3 101 - DIO4 102 103required: 104 - compatible 105 - reg 106 - interrupts 107 - spi-cpha 108 - spi-cpol 109 - spi-max-frequency 110 111allOf: 112 - $ref: /schemas/spi/spi-peripheral-props.yaml# 113 114unevaluatedProperties: false 115 116examples: 117 - | 118 #include <dt-bindings/interrupt-controller/irq.h> 119 spi { 120 #address-cells = <1>; 121 #size-cells = <0>; 122 123 imu@0 { 124 compatible = "adi,adis16495-1"; 125 reg = <0>; 126 spi-max-frequency = <3200000>; 127 spi-cpol; 128 spi-cpha; 129 interrupts = <25 IRQ_TYPE_EDGE_FALLING>; 130 interrupt-parent = <&gpio>; 131 interrupt-names = "DIO2"; 132 clocks = <&adis16495_sync>; 133 clock-names = "sync"; 134 adi,ext-clk-pin = "DIO1"; 135 }; 136 }; 137... 138