xref: /linux/Documentation/devicetree/bindings/iio/imu/adi,adis16480.yaml (revision 2a2dfc869d3345ccdd91322b023f4b0da84acbe7) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/iio/imu/adi,adis16480.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Analog Devices ADIS16480 and similar IMUs
8
9maintainers:
10  - Alexandru Tachici <alexandru.tachici@analog.com>
11
12properties:
13  compatible:
14    enum:
15      - adi,adis16375
16      - adi,adis16480
17      - adi,adis16485
18      - adi,adis16488
19      - adi,adis16490
20      - adi,adis16495-1
21      - adi,adis16495-2
22      - adi,adis16495-3
23      - adi,adis16497-1
24      - adi,adis16497-2
25      - adi,adis16497-3
26
27  reg:
28    maxItems: 1
29
30  interrupts:
31    minItems: 1
32    maxItems: 2
33    description: |
34      Accepted interrupt types are:
35      * IRQ_TYPE_EDGE_RISING
36      * IRQ_TYPE_EDGE_FALLING
37
38  interrupt-names:
39    minItems: 1
40    maxItems: 2
41    description:
42      Default if not supplied is DIO1.
43    items:
44      enum:
45        - DIO1
46        - DIO2
47        - DIO3
48        - DIO4
49
50  spi-max-frequency: true
51
52  spi-cpha: true
53  spi-cpol: true
54
55  reset-gpios:
56    maxItems: 1
57    description: Connected to RESET pin which is active low.
58
59  clocks:
60    maxItems: 1
61    description: If not provided, then the internal clock is used.
62
63  clock-names:
64    description: |
65      sync: In sync mode, the internal clock is disabled and the frequency
66            of the external clock signal establishes therate of data
67            collection and processing. See Fig 14 and 15 in the datasheet.
68            The clock-frequency must be:
69            * 3000 to 4500 Hz for adis1649x devices.
70            * 700 to 2400 Hz for adis1648x devices.
71      pps:  In Pulse Per Second (PPS) Mode, the rate of data collection and
72            production is equal to the product of the external clock
73            frequency and the scale factor in the SYNC_SCALE register, see
74            Table 154 in the datasheet.
75            The clock-frequency must be:
76            * 1 to 128 Hz for adis1649x devices.
77            * This mode is not supported by adis1648x devices.
78    enum:
79      - sync
80      - pps
81
82  adi,ext-clk-pin:
83    $ref: /schemas/types.yaml#/definitions/string
84    description: |
85      The DIOx line to be used as an external clock input.
86      Each DIOx pin supports only one function at a time (data ready line
87      selection or external clock input). When a single pin has two
88      two assignments, the enable bit for the lower priority function
89      automatically resets to zero (disabling the lower priority function).
90      Data ready has highest priority.
91      If not provided then DIO2 is assigned as default external clock
92      input pin.
93    enum:
94      - DIO1
95      - DIO2
96      - DIO3
97      - DIO4
98
99additionalProperties: false
100
101required:
102  - compatible
103  - reg
104  - interrupts
105  - spi-cpha
106  - spi-cpol
107  - spi-max-frequency
108
109examples:
110  - |
111    #include <dt-bindings/interrupt-controller/irq.h>
112    spi {
113        #address-cells = <1>;
114        #size-cells = <0>;
115
116        imu@0 {
117            compatible = "adi,adis16495-1";
118            reg = <0>;
119            spi-max-frequency = <3200000>;
120            spi-cpol;
121            spi-cpha;
122            interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
123            interrupt-parent = <&gpio>;
124            interrupt-names = "DIO2";
125            clocks = <&adis16495_sync>;
126            clock-names = "sync";
127            adi,ext-clk-pin = "DIO1";
128        };
129    };
130...
131