1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/iio/frequency/adi,adf4350.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Analog Devices ADF4350/ADF4351 wideband synthesizer 8 9maintainers: 10 - Michael Hennerich <michael.hennerich@analog.com> 11 12properties: 13 compatible: 14 enum: 15 - adi,adf4350 16 - adi,adf4351 17 18 reg: 19 maxItems: 1 20 21 spi-max-frequency: 22 maximum: 20000000 23 24 clocks: 25 maxItems: 1 26 description: Clock to provide CLKIN reference clock signal. 27 28 clock-names: 29 const: clkin 30 31 '#clock-cells': 32 const: 0 33 34 clock-output-names: 35 maxItems: 1 36 37 gpios: 38 maxItems: 1 39 description: Lock detect GPIO. 40 41 adi,channel-spacing: 42 $ref: /schemas/types.yaml#/definitions/uint32 43 description: 44 Channel spacing in Hz (influences MODULUS). 45 46 adi,power-up-frequency: 47 $ref: /schemas/types.yaml#/definitions/uint32 48 description: 49 If set the PLL tunes to this frequency (in Hz) on driver probe. 50 51 adi,reference-div-factor: 52 $ref: /schemas/types.yaml#/definitions/uint32 53 description: 54 If set the driver skips dynamic calculation and uses this default 55 value instead. 56 57 adi,reference-doubler-enable: 58 $ref: /schemas/types.yaml#/definitions/flag 59 description: Enables reference doubler. 60 61 adi,reference-div2-enable: 62 $ref: /schemas/types.yaml#/definitions/flag 63 description: Enables reference divider. 64 65 adi,phase-detector-polarity-positive-enable: 66 $ref: /schemas/types.yaml#/definitions/flag 67 description: Enables positive phase detector polarity. Default negative. 68 69 adi,lock-detect-precision-6ns-enable: 70 $ref: /schemas/types.yaml#/definitions/flag 71 description: Enables 6ns lock detect precision. Default = 10ns. 72 73 adi,lock-detect-function-integer-n-enable: 74 $ref: /schemas/types.yaml#/definitions/flag 75 description: 76 Enables lock detect for integer-N mode. Default = factional-N mode. 77 78 adi,charge-pump-current: 79 $ref: /schemas/types.yaml#/definitions/uint32 80 description: Charge pump current in mA. Default = 2500mA. 81 82 adi,muxout-select: 83 $ref: /schemas/types.yaml#/definitions/uint32 84 minimum: 0 85 maximum: 6 86 description: | 87 On chip multiplexer output selection. 88 Valid values for the multiplexer output are: 89 0: Three-State Output (default) 90 1: DVDD 91 2: DGND 92 3: R-Counter output 93 4: N-Divider output 94 5: Analog lock detect 95 6: Digital lock detect 96 97 adi,low-spur-mode-enable: 98 $ref: /schemas/types.yaml#/definitions/flag 99 description: Enables low spur mode. Default = Low noise mode. 100 101 adi,cycle-slip-reduction-enable: 102 $ref: /schemas/types.yaml#/definitions/flag 103 description: Enables cycle slip reduction. 104 105 adi,charge-cancellation-enable: 106 $ref: /schemas/types.yaml#/definitions/flag 107 description: 108 Enabled charge pump charge cancellation for integer-N modes. 109 110 adi,anti-backlash-3ns-enable: 111 $ref: /schemas/types.yaml#/definitions/flag 112 description: 113 Enables 3ns antibacklash pulse width for integer-N modes. 114 115 adi,band-select-clock-mode-high-enable: 116 $ref: /schemas/types.yaml#/definitions/flag 117 description: Enables faster band selection logic. 118 119 adi,12bit-clk-divider: 120 $ref: /schemas/types.yaml#/definitions/uint32 121 description: 122 Clock divider value used when adi,12bit-clkdiv-mode != 0 123 124 adi,clk-divider-mode: 125 $ref: /schemas/types.yaml#/definitions/uint32 126 enum: [0, 1, 2] 127 description: | 128 Valid values for the clkdiv mode are: 129 0: Clock divider off (default) 130 1: Fast lock enable 131 2: Phase resync enable 132 133 adi,aux-output-enable: 134 $ref: /schemas/types.yaml#/definitions/flag 135 description: Enables auxiliary RF output. 136 137 adi,aux-output-fundamental-enable: 138 $ref: /schemas/types.yaml#/definitions/flag 139 description: | 140 Selects fundamental VCO output on the auxiliary RF output. 141 Default = Output of RF dividers. 142 143 adi,mute-till-lock-enable: 144 $ref: /schemas/types.yaml#/definitions/flag 145 description: Enables Mute-Till-Lock-Detect function. 146 147 adi,output-power: 148 $ref: /schemas/types.yaml#/definitions/uint32 149 enum: [0, 1, 2, 3] 150 description: | 151 Output power selection. 152 Valid values for the power mode are: 153 0: -4dBm (default) 154 1: -1dBm 155 2: +2dBm 156 3: +5dBm 157 158 adi,aux-output-power: 159 $ref: /schemas/types.yaml#/definitions/uint32 160 enum: [0, 1, 2, 3] 161 description: | 162 Auxiliary output power selection. 163 Valid values for the power mode are: 164 0: -4dBm (default) 165 1: -1dBm 166 2: +2dBm 167 3: +5dBm 168 169required: 170 - compatible 171 - reg 172 - clocks 173 174allOf: 175 - $ref: /schemas/spi/spi-peripheral-props.yaml# 176 177unevaluatedProperties: false 178 179examples: 180 - | 181 spi { 182 #address-cells = <1>; 183 #size-cells = <0>; 184 185 pll@4 { 186 compatible = "adi,adf4351"; 187 reg = <4>; 188 spi-max-frequency = <10000000>; 189 clocks = <&clk0_ad9523 9>; 190 clock-names = "clkin"; 191 adi,channel-spacing = <10000>; 192 adi,power-up-frequency = <2400000000>; 193 adi,phase-detector-polarity-positive-enable; 194 adi,charge-pump-current = <2500>; 195 adi,output-power = <3>; 196 adi,mute-till-lock-enable; 197 }; 198 }; 199... 200