1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/iio/dac/adi,axi-dac.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Analog Devices AXI DAC IP core 8 9maintainers: 10 - Nuno Sa <nuno.sa@analog.com> 11 12description: | 13 Analog Devices Generic AXI DAC IP core for interfacing a DAC device 14 with a high speed serial (JESD204B/C) or source synchronous parallel 15 interface (LVDS/CMOS). 16 Usually, some other interface type (i.e SPI) is used as a control 17 interface for the actual DAC, while this IP core will interface 18 to the data-lines of the DAC and handle the streaming of data from 19 memory via DMA into the DAC. 20 21 https://wiki.analog.com/resources/fpga/docs/axi_dac_ip 22 https://analogdevicesinc.github.io/hdl/library/axi_ad3552r/index.html 23 24properties: 25 compatible: 26 enum: 27 - adi,axi-dac-9.1.b 28 - adi,axi-ad3552r 29 30 reg: 31 maxItems: 1 32 33 dmas: 34 maxItems: 1 35 36 dma-names: 37 items: 38 - const: tx 39 40 clocks: 41 minItems: 1 42 maxItems: 2 43 44 clock-names: 45 items: 46 - const: s_axi_aclk 47 - const: dac_clk 48 minItems: 1 49 50 '#io-backend-cells': 51 const: 0 52 53required: 54 - compatible 55 - dmas 56 - reg 57 - clocks 58 59allOf: 60 - if: 61 properties: 62 compatible: 63 contains: 64 const: adi,axi-ad3552r 65 then: 66 $ref: /schemas/spi/spi-controller.yaml# 67 properties: 68 clocks: 69 minItems: 2 70 clock-names: 71 minItems: 2 72 required: 73 - clock-names 74 else: 75 properties: 76 clocks: 77 maxItems: 1 78 clock-names: 79 maxItems: 1 80 81unevaluatedProperties: false 82 83examples: 84 - | 85 dac@44a00000 { 86 compatible = "adi,axi-dac-9.1.b"; 87 reg = <0x44a00000 0x10000>; 88 dmas = <&tx_dma 0>; 89 dma-names = "tx"; 90 #io-backend-cells = <0>; 91 clocks = <&clkc 15>; 92 clock-names = "s_axi_aclk"; 93 }; 94 95 - | 96 #include <dt-bindings/gpio/gpio.h> 97 axi_dac: spi@44a70000 { 98 compatible = "adi,axi-ad3552r"; 99 reg = <0x44a70000 0x1000>; 100 dmas = <&dac_tx_dma 0>; 101 dma-names = "tx"; 102 #io-backend-cells = <0>; 103 clocks = <&clkc 15>, <&ref_clk>; 104 clock-names = "s_axi_aclk", "dac_clk"; 105 106 #address-cells = <1>; 107 #size-cells = <0>; 108 109 dac@0 { 110 compatible = "adi,ad3552r"; 111 reg = <0>; 112 reset-gpios = <&gpio0 92 GPIO_ACTIVE_HIGH>; 113 io-backends = <&axi_dac>; 114 spi-max-frequency = <20000000>; 115 116 #address-cells = <1>; 117 #size-cells = <0>; 118 119 channel@0 { 120 reg = <0>; 121 adi,output-range-microvolt = <(-10000000) (10000000)>; 122 }; 123 }; 124 }; 125... 126