1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/iio/dac/adi,axi-dac.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Analog Devices AXI DAC IP core 8 9maintainers: 10 - Nuno Sa <nuno.sa@analog.com> 11 12description: | 13 Analog Devices Generic AXI DAC IP core for interfacing a DAC device 14 with a high speed serial (JESD204B/C) or source synchronous parallel 15 interface (LVDS/CMOS). 16 Usually, some other interface type (i.e SPI) is used as a control 17 interface for the actual DAC, while this IP core will interface 18 to the data-lines of the DAC and handle the streaming of data from 19 memory via DMA into the DAC. 20 21 https://wiki.analog.com/resources/fpga/docs/axi_dac_ip 22 23properties: 24 compatible: 25 enum: 26 - adi,axi-dac-9.1.b 27 28 reg: 29 maxItems: 1 30 31 dmas: 32 maxItems: 1 33 34 dma-names: 35 items: 36 - const: tx 37 38 clocks: 39 maxItems: 1 40 41 '#io-backend-cells': 42 const: 0 43 44required: 45 - compatible 46 - dmas 47 - reg 48 - clocks 49 50additionalProperties: false 51 52examples: 53 - | 54 dac@44a00000 { 55 compatible = "adi,axi-dac-9.1.b"; 56 reg = <0x44a00000 0x10000>; 57 dmas = <&tx_dma 0>; 58 dma-names = "tx"; 59 #io-backend-cells = <0>; 60 clocks = <&axi_clk>; 61 }; 62... 63