xref: /linux/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml (revision 8632987380765dee716d460640aa58d58d52998e) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: "http://devicetree.org/schemas/iio/adc/st,stm32-adc.yaml#"
5$schema: "http://devicetree.org/meta-schemas/core.yaml#"
6
7title: STMicroelectronics STM32 ADC bindings
8
9description: |
10  STM32 ADC is a successive approximation analog-to-digital converter.
11  It has several multiplexed input channels. Conversions can be performed
12  in single, continuous, scan or discontinuous mode. Result of the ADC is
13  stored in a left-aligned or right-aligned 32-bit data register.
14  Conversions can be launched in software or using hardware triggers.
15
16  The analog watchdog feature allows the application to detect if the input
17  voltage goes beyond the user-defined, higher or lower thresholds.
18
19  Each STM32 ADC block can have up to 3 ADC instances.
20
21maintainers:
22  - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
23
24properties:
25  compatible:
26    enum:
27      - st,stm32f4-adc-core
28      - st,stm32h7-adc-core
29      - st,stm32mp1-adc-core
30
31  reg:
32    maxItems: 1
33
34  interrupts:
35    description: |
36      One or more interrupts for ADC block, depending on part used:
37        - stm32f4 and stm32h7 share a common ADC interrupt line.
38        - stm32mp1 has two separate interrupt lines, one for each ADC within
39          ADC block.
40    minItems: 1
41    maxItems: 2
42
43  clocks:
44    minItems: 1
45    maxItems: 2
46    description: |
47      Core can use up to two clocks, depending on part used:
48        - "adc" clock: for the analog circuitry, common to all ADCs.
49          It's required on stm32f4.
50          It's optional on stm32h7 and stm32mp1.
51        - "bus" clock: for registers access, common to all ADCs.
52          It's not present on stm32f4.
53          It's required on stm32h7 and stm32mp1.
54
55  clock-names: true
56
57  st,max-clk-rate-hz:
58    description:
59      Allow to specify desired max clock rate used by analog circuitry.
60
61  vdda-supply:
62    description: Phandle to the vdda input analog voltage.
63
64  vref-supply:
65    description: Phandle to the vref input analog reference voltage.
66
67  booster-supply:
68    description:
69      Phandle to the embedded booster regulator that can be used to supply ADC
70      analog input switches on stm32h7 and stm32mp1.
71
72  vdd-supply:
73    description:
74      Phandle to the vdd input voltage. It can be used to supply ADC analog
75      input switches on stm32mp1.
76
77  st,syscfg:
78    description:
79      Phandle to system configuration controller. It can be used to control the
80      analog circuitry on stm32mp1.
81    $ref: "/schemas/types.yaml#/definitions/phandle-array"
82
83  interrupt-controller: true
84
85  '#interrupt-cells':
86    const: 1
87
88  '#address-cells':
89    const: 1
90
91  '#size-cells':
92    const: 0
93
94allOf:
95  - if:
96      properties:
97        compatible:
98          contains:
99            const: st,stm32f4-adc-core
100
101    then:
102      properties:
103        clocks:
104          maxItems: 1
105
106        clock-names:
107          const: adc
108
109        interrupts:
110          items:
111            - description: interrupt line common for all ADCs
112
113        st,max-clk-rate-hz:
114          minimum: 600000
115          maximum: 36000000
116          default: 36000000
117
118        booster-supply: false
119
120        vdd-supply: false
121
122        st,syscfg: false
123
124  - if:
125      properties:
126        compatible:
127          contains:
128            const: st,stm32h7-adc-core
129
130    then:
131      properties:
132        clocks:
133          minItems: 1
134          maxItems: 2
135
136        clock-names:
137          items:
138            - const: bus
139            - const: adc
140          minItems: 1
141          maxItems: 2
142
143        interrupts:
144          items:
145            - description: interrupt line common for all ADCs
146
147        st,max-clk-rate-hz:
148          minimum: 120000
149          maximum: 36000000
150          default: 36000000
151
152        vdd-supply: false
153
154        st,syscfg: false
155
156  - if:
157      properties:
158        compatible:
159          contains:
160            const: st,stm32mp1-adc-core
161
162    then:
163      properties:
164        clocks:
165          minItems: 1
166          maxItems: 2
167
168        clock-names:
169          items:
170            - const: bus
171            - const: adc
172          minItems: 1
173          maxItems: 2
174
175        interrupts:
176          items:
177            - description: interrupt line for ADC1
178            - description: interrupt line for ADC2
179
180        st,max-clk-rate-hz:
181          minimum: 120000
182          maximum: 36000000
183          default: 36000000
184
185additionalProperties: false
186
187required:
188  - compatible
189  - reg
190  - interrupts
191  - clocks
192  - clock-names
193  - vdda-supply
194  - vref-supply
195  - interrupt-controller
196  - '#interrupt-cells'
197  - '#address-cells'
198  - '#size-cells'
199
200patternProperties:
201  "^adc@[0-9]+$":
202    type: object
203    description:
204      An ADC block node should contain at least one subnode, representing an
205      ADC instance available on the machine.
206
207    properties:
208      compatible:
209        enum:
210          - st,stm32f4-adc
211          - st,stm32h7-adc
212          - st,stm32mp1-adc
213
214      reg:
215        description: |
216          Offset of ADC instance in ADC block. Valid values are:
217            - 0x0:   ADC1
218            - 0x100: ADC2
219            - 0x200: ADC3 (stm32f4 only)
220        maxItems: 1
221
222      '#io-channel-cells':
223        const: 1
224
225      '#address-cells':
226        const: 1
227
228      '#size-cells':
229        const: 0
230
231      interrupts:
232        description: |
233          IRQ Line for the ADC instance. Valid values are:
234            - 0 for adc@0
235            - 1 for adc@100
236            - 2 for adc@200 (stm32f4 only)
237        maxItems: 1
238
239      clocks:
240        description:
241          Input clock private to this ADC instance. It's required only on
242          stm32f4, that has per instance clock input for registers access.
243        maxItems: 1
244
245      dmas:
246        description: RX DMA Channel
247        maxItems: 1
248
249      dma-names:
250        const: rx
251
252      assigned-resolution-bits:
253        description: |
254          Resolution (bits) to use for conversions:
255            - can be 6, 8, 10 or 12 on stm32f4
256            - can be 8, 10, 12, 14 or 16 on stm32h7 and stm32mp1
257
258      st,adc-channels:
259        description: |
260          List of single-ended channels muxed for this ADC. It can have up to:
261            - 16 channels, numbered from 0 to 15 (for in0..in15) on stm32f4
262            - 20 channels, numbered from 0 to 19 (for in0..in19) on stm32h7 and
263              stm32mp1.
264        $ref: /schemas/types.yaml#/definitions/uint32-array
265        deprecated: true
266
267      st,adc-diff-channels:
268        description: |
269          List of differential channels muxed for this ADC. Some channels can
270          be configured as differential instead of single-ended on stm32h7 and
271          on stm32mp1. Positive and negative inputs pairs are listed:
272          <vinp vinn>, <vinp vinn>,... vinp and vinn are numbered from 0 to 19.
273
274          Note: At least one of "st,adc-channels" or "st,adc-diff-channels" is
275          required if no adc generic channel is defined. These legacy channel
276          properties are exclusive with adc generic channel bindings.
277          Both properties can be used together. Some channels can be
278          used as single-ended and some other ones as differential (mixed). But
279          channels can't be configured both as single-ended and differential.
280        $ref: /schemas/types.yaml#/definitions/uint32-matrix
281        items:
282          items:
283            - description: |
284                "vinp" indicates positive input number
285              minimum: 0
286              maximum: 19
287            - description: |
288                "vinn" indicates negative input number
289              minimum: 0
290              maximum: 19
291        deprecated: true
292
293      st,min-sample-time-nsecs:
294        description:
295          Minimum sampling time in nanoseconds. Depending on hardware (board)
296          e.g. high/low analog input source impedance, fine tune of ADC
297          sampling time may be recommended. This can be either one value or an
298          array that matches "st,adc-channels" and/or "st,adc-diff-channels"
299          list, to set sample time resp. for all channels, or independently for
300          each channel.
301        $ref: /schemas/types.yaml#/definitions/uint32-array
302        deprecated: true
303
304      nvmem-cells:
305        items:
306          - description: Phandle to the calibration vrefint data provided by otp
307
308      nvmem-cell-names:
309        items:
310          - const: vrefint
311
312    patternProperties:
313      "^channel@([0-9]|1[0-9])$":
314        type: object
315        $ref: "adc.yaml"
316        description: Represents the external channels which are connected to the ADC.
317
318        properties:
319          reg:
320            items:
321              minimum: 0
322              maximum: 19
323
324          label:
325            description: |
326              Unique name to identify which channel this is.
327              Reserved label names "vddcore", "vrefint" and "vbat"
328              are used to identify internal channels with matching names.
329
330          diff-channels:
331            $ref: /schemas/types.yaml#/definitions/uint32-array
332            items:
333              minimum: 0
334              maximum: 19
335
336          st,min-sample-time-ns:
337            description: |
338              Minimum sampling time in nanoseconds. Depending on hardware (board)
339              e.g. high/low analog input source impedance, fine tune of ADC
340              sampling time may be recommended.
341
342        required:
343          - reg
344
345        additionalProperties: false
346
347    allOf:
348      - if:
349          properties:
350            compatible:
351              contains:
352                const: st,stm32f4-adc
353
354        then:
355          properties:
356            reg:
357              enum:
358                - 0x0
359                - 0x100
360                - 0x200
361
362            interrupts:
363              minimum: 0
364              maximum: 2
365
366            assigned-resolution-bits:
367              enum: [6, 8, 10, 12]
368              default: 12
369
370            st,adc-channels:
371              minItems: 1
372              maxItems: 16
373              items:
374                minimum: 0
375                maximum: 15
376
377            st,adc-diff-channels: false
378
379            st,min-sample-time-nsecs:
380              minItems: 1
381              maxItems: 16
382              items:
383                minimum: 80
384
385          required:
386            - clocks
387
388      - if:
389          properties:
390            compatible:
391              contains:
392                enum:
393                  - st,stm32h7-adc
394                  - st,stm32mp1-adc
395
396        then:
397          properties:
398            reg:
399              enum:
400                - 0x0
401                - 0x100
402
403            interrupts:
404              minimum: 0
405              maximum: 1
406
407            assigned-resolution-bits:
408              enum: [8, 10, 12, 14, 16]
409              default: 16
410
411            st,adc-channels:
412              minItems: 1
413              maxItems: 20
414              items:
415                minimum: 0
416                maximum: 19
417
418            st,min-sample-time-nsecs:
419              minItems: 1
420              maxItems: 20
421              items:
422                minimum: 40
423
424    additionalProperties: false
425
426    required:
427      - compatible
428      - reg
429      - interrupts
430      - '#io-channel-cells'
431
432examples:
433  - |
434    // Example 1: with stm32f429, ADC1, single-ended channel 8
435      adc123: adc@40012000 {
436        compatible = "st,stm32f4-adc-core";
437        reg = <0x40012000 0x400>;
438        interrupts = <18>;
439        clocks = <&rcc 0 168>;
440        clock-names = "adc";
441        st,max-clk-rate-hz = <36000000>;
442        vdda-supply = <&vdda>;
443        vref-supply = <&vref>;
444        interrupt-controller;
445        #interrupt-cells = <1>;
446        #address-cells = <1>;
447        #size-cells = <0>;
448        adc@0 {
449          compatible = "st,stm32f4-adc";
450          #io-channel-cells = <1>;
451          reg = <0x0>;
452          clocks = <&rcc 0 168>;
453          interrupt-parent = <&adc123>;
454          interrupts = <0>;
455          st,adc-channels = <8>;
456          dmas = <&dma2 0 0 0x400 0x0>;
457          dma-names = "rx";
458          assigned-resolution-bits = <8>;
459        };
460        // ...
461        // other adc child nodes follow...
462      };
463
464  - |
465    // Example 2: with stm32mp157c to setup ADC1 with:
466    // - channels 0 & 1 as single-ended
467    // - channels 2 & 3 as differential (with resp. 6 & 7 negative inputs)
468      #include <dt-bindings/interrupt-controller/arm-gic.h>
469      #include <dt-bindings/clock/stm32mp1-clks.h>
470      adc12: adc@48003000 {
471        compatible = "st,stm32mp1-adc-core";
472        reg = <0x48003000 0x400>;
473        interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
474                     <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
475        clocks = <&rcc ADC12>, <&rcc ADC12_K>;
476        clock-names = "bus", "adc";
477        booster-supply = <&booster>;
478        vdd-supply = <&vdd>;
479        vdda-supply = <&vdda>;
480        vref-supply = <&vref>;
481        st,syscfg = <&syscfg>;
482        interrupt-controller;
483        #interrupt-cells = <1>;
484        #address-cells = <1>;
485        #size-cells = <0>;
486        adc@0 {
487          compatible = "st,stm32mp1-adc";
488          #io-channel-cells = <1>;
489          reg = <0x0>;
490          interrupt-parent = <&adc12>;
491          interrupts = <0>;
492          st,adc-channels = <0 1>;
493          st,adc-diff-channels = <2 6>, <3 7>;
494          st,min-sample-time-nsecs = <5000>;
495          dmas = <&dmamux1 9 0x400 0x05>;
496          dma-names = "rx";
497        };
498        // ...
499        // other adc child node follow...
500      };
501
502  - |
503    // Example 3: with stm32mp157c to setup ADC2 with:
504    // - internal channels 13, 14, 15.
505      #include <dt-bindings/interrupt-controller/arm-gic.h>
506      #include <dt-bindings/clock/stm32mp1-clks.h>
507      adc122: adc@48003000 {
508        compatible = "st,stm32mp1-adc-core";
509        reg = <0x48003000 0x400>;
510        interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
511                     <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
512        clocks = <&rcc ADC12>, <&rcc ADC12_K>;
513        clock-names = "bus", "adc";
514        booster-supply = <&booster>;
515        vdd-supply = <&vdd>;
516        vdda-supply = <&vdda>;
517        vref-supply = <&vref>;
518        st,syscfg = <&syscfg>;
519        interrupt-controller;
520        #interrupt-cells = <1>;
521        #address-cells = <1>;
522        #size-cells = <0>;
523        adc@100 {
524          compatible = "st,stm32mp1-adc";
525          #io-channel-cells = <1>;
526          reg = <0x100>;
527          interrupts = <1>;
528          #address-cells = <1>;
529          #size-cells = <0>;
530          channel@13 {
531            reg = <13>;
532            label = "vrefint";
533            st,min-sample-time-ns = <9000>;
534          };
535          channel@14 {
536            reg = <14>;
537            label = "vddcore";
538            st,min-sample-time-ns = <9000>;
539          };
540          channel@15 {
541            reg = <15>;
542            label = "vbat";
543            st,min-sample-time-ns = <9000>;
544          };
545        };
546      };
547
548...
549