xref: /linux/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml (revision 0c8ea05e9b3d8e5287e2a968f2a2e744dfd31b99) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/iio/adc/st,stm32-adc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: STMicroelectronics STM32 ADC
8
9description: |
10  STM32 ADC is a successive approximation analog-to-digital converter.
11  It has several multiplexed input channels. Conversions can be performed
12  in single, continuous, scan or discontinuous mode. Result of the ADC is
13  stored in a left-aligned or right-aligned 32-bit data register.
14  Conversions can be launched in software or using hardware triggers.
15
16  The analog watchdog feature allows the application to detect if the input
17  voltage goes beyond the user-defined, higher or lower thresholds.
18
19  Each STM32 ADC block can have up to 3 ADC instances.
20
21maintainers:
22  - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
23
24properties:
25  compatible:
26    enum:
27      - st,stm32f4-adc-core
28      - st,stm32h7-adc-core
29      - st,stm32mp1-adc-core
30      - st,stm32mp13-adc-core
31
32  reg:
33    maxItems: 1
34
35  interrupts:
36    description: |
37      One or more interrupts for ADC block, depending on part used:
38        - stm32f4 and stm32h7 share a common ADC interrupt line.
39        - stm32mp1 has two separate interrupt lines, one for each ADC within
40          ADC block.
41        - stm32mp13 has an interrupt line per ADC block.
42    minItems: 1
43    maxItems: 2
44
45  clocks:
46    minItems: 1
47    maxItems: 2
48    description: |
49      Core can use up to two clocks, depending on part used:
50        - "adc" clock: for the analog circuitry, common to all ADCs.
51          It's required on stm32f4.
52          It's optional on stm32h7 and stm32mp1.
53        - "bus" clock: for registers access, common to all ADCs.
54          It's not present on stm32f4.
55          It's required on stm32h7 and stm32mp1.
56
57  clock-names: true
58
59  st,max-clk-rate-hz:
60    description:
61      Allow to specify desired max clock rate used by analog circuitry.
62
63  vdda-supply:
64    description: Phandle to the vdda input analog voltage.
65
66  vref-supply:
67    description: Phandle to the vref input analog reference voltage.
68
69  booster-supply:
70    description:
71      Phandle to the embedded booster regulator that can be used to supply ADC
72      analog input switches on stm32h7 and stm32mp1.
73
74  vdd-supply:
75    description:
76      Phandle to the vdd input voltage. It can be used to supply ADC analog
77      input switches on stm32mp1.
78
79  st,syscfg:
80    description:
81      Phandle to system configuration controller. It can be used to control the
82      analog circuitry on stm32mp1.
83    $ref: /schemas/types.yaml#/definitions/phandle-array
84
85  interrupt-controller: true
86
87  '#interrupt-cells':
88    const: 1
89
90  '#address-cells':
91    const: 1
92
93  '#size-cells':
94    const: 0
95
96  access-controllers:
97    minItems: 1
98    maxItems: 2
99
100allOf:
101  - if:
102      properties:
103        compatible:
104          contains:
105            const: st,stm32f4-adc-core
106
107    then:
108      properties:
109        clocks:
110          maxItems: 1
111
112        clock-names:
113          const: adc
114
115        interrupts:
116          items:
117            - description: interrupt line common for all ADCs
118
119        st,max-clk-rate-hz:
120          minimum: 600000
121          maximum: 36000000
122          default: 36000000
123
124        booster-supply: false
125
126        vdd-supply: false
127
128        st,syscfg: false
129
130  - if:
131      properties:
132        compatible:
133          contains:
134            const: st,stm32h7-adc-core
135
136    then:
137      properties:
138        clocks:
139          minItems: 1
140          maxItems: 2
141
142        clock-names:
143          items:
144            - const: bus
145            - const: adc
146          minItems: 1
147
148        interrupts:
149          items:
150            - description: interrupt line common for all ADCs
151
152        st,max-clk-rate-hz:
153          minimum: 120000
154          maximum: 36000000
155          default: 36000000
156
157        vdd-supply: false
158
159        st,syscfg: false
160
161  - if:
162      properties:
163        compatible:
164          contains:
165            const: st,stm32mp1-adc-core
166
167    then:
168      properties:
169        clocks:
170          minItems: 1
171          maxItems: 2
172
173        clock-names:
174          items:
175            - const: bus
176            - const: adc
177          minItems: 1
178
179        interrupts:
180          items:
181            - description: interrupt line for ADC1
182            - description: interrupt line for ADC2
183
184        st,max-clk-rate-hz:
185          minimum: 120000
186          maximum: 36000000
187          default: 36000000
188
189  - if:
190      properties:
191        compatible:
192          contains:
193            const: st,stm32mp13-adc-core
194
195    then:
196      properties:
197        clocks:
198          minItems: 1
199          maxItems: 2
200
201        clock-names:
202          items:
203            - const: bus
204            - const: adc
205          minItems: 1
206
207        interrupts:
208          items:
209            - description: ADC interrupt line
210
211        st,max-clk-rate-hz:
212          minimum: 150000
213          maximum: 75000000
214          default: 75000000
215
216additionalProperties: false
217
218required:
219  - compatible
220  - reg
221  - interrupts
222  - clocks
223  - clock-names
224  - vdda-supply
225  - vref-supply
226  - interrupt-controller
227  - '#interrupt-cells'
228  - '#address-cells'
229  - '#size-cells'
230
231patternProperties:
232  "^adc@[0-9]+$":
233    type: object
234    description:
235      An ADC block node should contain at least one subnode, representing an
236      ADC instance available on the machine.
237
238    properties:
239      compatible:
240        enum:
241          - st,stm32f4-adc
242          - st,stm32h7-adc
243          - st,stm32mp1-adc
244          - st,stm32mp13-adc
245
246      reg:
247        description: |
248          Offset of ADC instance in ADC block. Valid values are:
249            - 0x0:   ADC1
250            - 0x100: ADC2
251            - 0x200: ADC3 (stm32f4 only)
252        maxItems: 1
253
254      '#io-channel-cells':
255        const: 1
256
257      '#address-cells':
258        const: 1
259
260      '#size-cells':
261        const: 0
262
263      interrupts:
264        description: |
265          IRQ Line for the ADC instance. Valid values are:
266            - 0 for adc@0 (single adc for stm32mp13)
267            - 1 for adc@100
268            - 2 for adc@200 (stm32f4 only)
269        maxItems: 1
270
271      clocks:
272        description:
273          Input clock private to this ADC instance. It's required only on
274          stm32f4, that has per instance clock input for registers access.
275        maxItems: 1
276
277      dmas:
278        description: RX DMA Channel
279        maxItems: 1
280
281      dma-names:
282        const: rx
283
284      assigned-resolution-bits:
285        description: |
286          Resolution (bits) to use for conversions:
287            - can be 6, 8, 10 or 12 on stm32f4 and stm32mp13
288            - can be 8, 10, 12, 14 or 16 on stm32h7 and stm32mp1
289
290      st,adc-channels:
291        description: |
292          List of single-ended channels muxed for this ADC. It can have up to:
293            - 16 channels, numbered from 0 to 15 (for in0..in15) on stm32f4
294            - 19 channels, numbered from 0 to 18 (for in0..in18) on stm32mp13.
295            - 20 channels, numbered from 0 to 19 (for in0..in19) on stm32h7 and
296              stm32mp1.
297        $ref: /schemas/types.yaml#/definitions/uint32-array
298        deprecated: true
299
300      st,adc-diff-channels:
301        description: |
302          List of differential channels muxed for this ADC. Some channels can
303          be configured as differential instead of single-ended on stm32h7 and
304          on stm32mp1. Positive and negative inputs pairs are listed:
305          <vinp vinn>, <vinp vinn>,... vinp and vinn are numbered from 0 to 19.
306
307          Note: At least one of "st,adc-channels" or "st,adc-diff-channels" is
308          required if no adc generic channel is defined. These legacy channel
309          properties are exclusive with adc generic channel bindings.
310          Both properties can be used together. Some channels can be
311          used as single-ended and some other ones as differential (mixed). But
312          channels can't be configured both as single-ended and differential.
313        $ref: /schemas/types.yaml#/definitions/uint32-matrix
314        items:
315          items:
316            - description: |
317                "vinp" indicates positive input number
318              minimum: 0
319              maximum: 19
320            - description: |
321                "vinn" indicates negative input number
322              minimum: 0
323              maximum: 19
324        deprecated: true
325
326      st,min-sample-time-nsecs:
327        description:
328          Minimum sampling time in nanoseconds. Depending on hardware (board)
329          e.g. high/low analog input source impedance, fine tune of ADC
330          sampling time may be recommended. This can be either one value or an
331          array that matches "st,adc-channels" and/or "st,adc-diff-channels"
332          list, to set sample time resp. for all channels, or independently for
333          each channel.
334        $ref: /schemas/types.yaml#/definitions/uint32-array
335        deprecated: true
336
337      nvmem-cells:
338        items:
339          - description: Phandle to the calibration vrefint data provided by otp
340
341      nvmem-cell-names:
342        items:
343          - const: vrefint
344
345    patternProperties:
346      "^channel@([0-9]|1[0-9])$":
347        type: object
348        $ref: adc.yaml
349        description: Represents the external channels which are connected to the ADC.
350
351        properties:
352          reg:
353            items:
354              minimum: 0
355              maximum: 19
356
357          label:
358            description: |
359              Unique name to identify which channel this is.
360              Reserved label names "vddcore", "vddcpu", "vddq_ddr", "vrefint" and "vbat"
361              are used to identify internal channels with matching names.
362
363          diff-channels:
364            $ref: /schemas/types.yaml#/definitions/uint32-array
365            items:
366              minimum: 0
367              maximum: 19
368
369          st,min-sample-time-ns:
370            description: |
371              Minimum sampling time in nanoseconds. Depending on hardware (board)
372              e.g. high/low analog input source impedance, fine tune of ADC
373              sampling time may be recommended.
374
375        required:
376          - reg
377
378        additionalProperties: false
379
380    allOf:
381      - if:
382          properties:
383            compatible:
384              contains:
385                const: st,stm32f4-adc
386
387        then:
388          properties:
389            reg:
390              enum:
391                - 0x0
392                - 0x100
393                - 0x200
394
395            interrupts:
396              minimum: 0
397              maximum: 2
398
399            assigned-resolution-bits:
400              enum: [6, 8, 10, 12]
401              default: 12
402
403            st,adc-channels:
404              minItems: 1
405              maxItems: 16
406              items:
407                minimum: 0
408                maximum: 15
409
410            st,adc-diff-channels: false
411
412            st,min-sample-time-nsecs:
413              minItems: 1
414              maxItems: 16
415              items:
416                minimum: 80
417
418          required:
419            - clocks
420
421      - if:
422          properties:
423            compatible:
424              contains:
425                enum:
426                  - st,stm32h7-adc
427                  - st,stm32mp1-adc
428
429        then:
430          properties:
431            reg:
432              enum:
433                - 0x0
434                - 0x100
435
436            interrupts:
437              minimum: 0
438              maximum: 1
439
440            assigned-resolution-bits:
441              enum: [8, 10, 12, 14, 16]
442              default: 16
443
444            st,adc-channels:
445              minItems: 1
446              maxItems: 20
447              items:
448                minimum: 0
449                maximum: 19
450
451            st,min-sample-time-nsecs:
452              minItems: 1
453              maxItems: 20
454              items:
455                minimum: 40
456
457
458      - if:
459          properties:
460            compatible:
461              contains:
462                const: st,stm32mp13-adc
463
464        then:
465          properties:
466            reg:
467              const: 0x0
468
469            interrupts:
470              const: 0
471
472            assigned-resolution-bits:
473              enum: [6, 8, 10, 12]
474              default: 12
475
476            st,adc-channels:
477              minItems: 1
478              maxItems: 19
479              items:
480                minimum: 0
481                maximum: 18
482
483            st,min-sample-time-nsecs:
484              minItems: 1
485              maxItems: 19
486              items:
487                minimum: 40
488    additionalProperties: false
489
490    required:
491      - compatible
492      - reg
493      - interrupts
494      - '#io-channel-cells'
495
496examples:
497  - |
498    // Example 1: with stm32f429, ADC1, single-ended channel 8
499      adc123: adc@40012000 {
500        compatible = "st,stm32f4-adc-core";
501        reg = <0x40012000 0x400>;
502        interrupts = <18>;
503        clocks = <&rcc 0 168>;
504        clock-names = "adc";
505        st,max-clk-rate-hz = <36000000>;
506        vdda-supply = <&vdda>;
507        vref-supply = <&vref>;
508        interrupt-controller;
509        #interrupt-cells = <1>;
510        #address-cells = <1>;
511        #size-cells = <0>;
512        adc@0 {
513          compatible = "st,stm32f4-adc";
514          #io-channel-cells = <1>;
515          reg = <0x0>;
516          clocks = <&rcc 0 168>;
517          interrupt-parent = <&adc123>;
518          interrupts = <0>;
519          st,adc-channels = <8>;
520          dmas = <&dma2 0 0 0x400 0x0>;
521          dma-names = "rx";
522          assigned-resolution-bits = <8>;
523        };
524        // ...
525        // other adc child nodes follow...
526      };
527
528  - |
529    // Example 2: with stm32mp157c to setup ADC1 with:
530    // - channels 0 & 1 as single-ended
531    // - channels 2 & 3 as differential (with resp. 6 & 7 negative inputs)
532      #include <dt-bindings/interrupt-controller/arm-gic.h>
533      #include <dt-bindings/clock/stm32mp1-clks.h>
534      adc12: adc@48003000 {
535        compatible = "st,stm32mp1-adc-core";
536        reg = <0x48003000 0x400>;
537        interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
538                     <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
539        clocks = <&rcc ADC12>, <&rcc ADC12_K>;
540        clock-names = "bus", "adc";
541        booster-supply = <&booster>;
542        vdd-supply = <&vdd>;
543        vdda-supply = <&vdda>;
544        vref-supply = <&vref>;
545        st,syscfg = <&syscfg>;
546        interrupt-controller;
547        #interrupt-cells = <1>;
548        #address-cells = <1>;
549        #size-cells = <0>;
550        adc@0 {
551          compatible = "st,stm32mp1-adc";
552          #io-channel-cells = <1>;
553          reg = <0x0>;
554          interrupt-parent = <&adc12>;
555          interrupts = <0>;
556          st,adc-channels = <0 1>;
557          st,adc-diff-channels = <2 6>, <3 7>;
558          st,min-sample-time-nsecs = <5000>;
559          dmas = <&dmamux1 9 0x400 0x05>;
560          dma-names = "rx";
561        };
562        // ...
563        // other adc child node follow...
564      };
565
566  - |
567    // Example 3: with stm32mp157c to setup ADC2 with:
568    // - internal channels 13, 14, 15.
569      #include <dt-bindings/interrupt-controller/arm-gic.h>
570      #include <dt-bindings/clock/stm32mp1-clks.h>
571      adc122: adc@48003000 {
572        compatible = "st,stm32mp1-adc-core";
573        reg = <0x48003000 0x400>;
574        interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
575                     <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
576        clocks = <&rcc ADC12>, <&rcc ADC12_K>;
577        clock-names = "bus", "adc";
578        booster-supply = <&booster>;
579        vdd-supply = <&vdd>;
580        vdda-supply = <&vdda>;
581        vref-supply = <&vref>;
582        st,syscfg = <&syscfg>;
583        interrupt-controller;
584        #interrupt-cells = <1>;
585        #address-cells = <1>;
586        #size-cells = <0>;
587        adc@100 {
588          compatible = "st,stm32mp1-adc";
589          #io-channel-cells = <1>;
590          reg = <0x100>;
591          interrupts = <1>;
592          #address-cells = <1>;
593          #size-cells = <0>;
594          channel@13 {
595            reg = <13>;
596            label = "vrefint";
597            st,min-sample-time-ns = <9000>;
598          };
599          channel@14 {
600            reg = <14>;
601            label = "vddcore";
602            st,min-sample-time-ns = <9000>;
603          };
604          channel@15 {
605            reg = <15>;
606            label = "vbat";
607            st,min-sample-time-ns = <9000>;
608          };
609        };
610      };
611
612...
613