xref: /linux/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml (revision 24168c5e6dfbdd5b414f048f47f75d64533296ca) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/iio/adc/renesas,rzg2l-adc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas RZ/G2L ADC
8
9maintainers:
10  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
11
12description: |
13  A/D Converter block is a successive approximation analog-to-digital converter
14  with a 12-bit accuracy. Up to eight analog input channels can be selected.
15  Conversions can be performed in single or repeat mode. Result of the ADC is
16  stored in a 32-bit data register corresponding to each channel.
17
18properties:
19  compatible:
20    items:
21      - enum:
22          - renesas,r9a07g043-adc   # RZ/G2UL and RZ/Five
23          - renesas,r9a07g044-adc   # RZ/G2L
24          - renesas,r9a07g054-adc   # RZ/V2L
25      - const: renesas,rzg2l-adc
26
27  reg:
28    maxItems: 1
29
30  interrupts:
31    maxItems: 1
32
33  clocks:
34    items:
35      - description: converter clock
36      - description: peripheral clock
37
38  clock-names:
39    items:
40      - const: adclk
41      - const: pclk
42
43  power-domains:
44    maxItems: 1
45
46  resets:
47    maxItems: 2
48
49  reset-names:
50    items:
51      - const: presetn
52      - const: adrst-n
53
54  '#address-cells':
55    const: 1
56
57  '#size-cells':
58    const: 0
59
60required:
61  - compatible
62  - reg
63  - interrupts
64  - clocks
65  - clock-names
66  - power-domains
67  - resets
68  - reset-names
69
70patternProperties:
71  "^channel@[0-7]$":
72    $ref: adc.yaml
73    type: object
74    description: |
75      Represents the external channels which are connected to the ADC.
76
77    properties:
78      reg:
79        description: |
80          The channel number.
81
82    required:
83      - reg
84
85    additionalProperties: false
86
87allOf:
88  - if:
89      properties:
90        compatible:
91          contains:
92            const: renesas,r9a07g043-adc
93    then:
94      patternProperties:
95        "^channel@[2-7]$": false
96        "^channel@[0-1]$":
97          properties:
98            reg:
99              minimum: 0
100              maximum: 1
101    else:
102      patternProperties:
103        "^channel@[0-7]$":
104          properties:
105            reg:
106              minimum: 0
107              maximum: 7
108
109additionalProperties: false
110
111examples:
112  - |
113    #include <dt-bindings/clock/r9a07g044-cpg.h>
114    #include <dt-bindings/interrupt-controller/arm-gic.h>
115
116    adc: adc@10059000 {
117      compatible = "renesas,r9a07g044-adc", "renesas,rzg2l-adc";
118      reg = <0x10059000 0x400>;
119      interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
120      clocks = <&cpg CPG_MOD R9A07G044_ADC_ADCLK>,
121               <&cpg CPG_MOD R9A07G044_ADC_PCLK>;
122      clock-names = "adclk", "pclk";
123      power-domains = <&cpg>;
124      resets = <&cpg R9A07G044_ADC_PRESETN>,
125               <&cpg R9A07G044_ADC_ADRST_N>;
126      reset-names = "presetn", "adrst-n";
127
128      #address-cells = <1>;
129      #size-cells = <0>;
130
131      channel@0 {
132        reg = <0>;
133      };
134      channel@1 {
135        reg = <1>;
136      };
137      channel@2 {
138        reg = <2>;
139      };
140      channel@3 {
141        reg = <3>;
142      };
143      channel@4 {
144        reg = <4>;
145      };
146      channel@5 {
147        reg = <5>;
148      };
149      channel@6 {
150        reg = <6>;
151      };
152      channel@7 {
153        reg = <7>;
154      };
155    };
156