xref: /linux/Documentation/devicetree/bindings/iio/adc/ingenic,adc.yaml (revision 1644d755d0b06d0f1ee93e1c44336c29386546b4) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2# Copyright 2019-2020 Artur Rojek
3%YAML 1.2
4---
5$id: "http://devicetree.org/schemas/iio/adc/ingenic,adc.yaml#"
6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7
8title: Ingenic JZ47xx ADC controller IIO
9
10maintainers:
11  - Artur Rojek <contact@artur-rojek.eu>
12
13description: >
14  Industrial I/O subsystem bindings for ADC controller found in
15  Ingenic JZ47xx SoCs.
16
17  ADC clients must use the format described in
18  https://github.com/devicetree-org/dt-schema/blob/master/schemas/iio/iio-consumer.yaml,
19  giving a phandle and IIO specifier pair ("io-channels") to the ADC controller.
20
21properties:
22  compatible:
23    enum:
24      - ingenic,jz4725b-adc
25      - ingenic,jz4740-adc
26      - ingenic,jz4760-adc
27      - ingenic,jz4760b-adc
28      - ingenic,jz4770-adc
29
30  '#io-channel-cells':
31    const: 1
32    description:
33      Must be set to <1> to indicate channels are selected by index.
34
35  reg:
36    maxItems: 1
37
38  clocks:
39    maxItems: 1
40
41  clock-names:
42    items:
43      - const: adc
44
45  interrupts:
46    maxItems: 1
47
48  ingenic,use-internal-divider:
49    description:
50      If present, battery voltage is read from the VBAT_IR pin, which has an
51      internal 1/4 divider. If absent, it is read through the VBAT_ER pin,
52      which does not have such a divider.
53    type: boolean
54
55if:
56  not:
57    properties:
58      compatible:
59        contains:
60          const: ingenic,jz4760b-adc
61then:
62  properties:
63    ingenic,use-internal-divider: false
64
65required:
66  - compatible
67  - '#io-channel-cells'
68  - reg
69  - clocks
70  - clock-names
71  - interrupts
72
73additionalProperties: false
74
75examples:
76  - |
77    #include <dt-bindings/clock/ingenic,jz4740-cgu.h>
78    #include <dt-bindings/iio/adc/ingenic,adc.h>
79
80    adc@10070000 {
81            compatible = "ingenic,jz4740-adc";
82            #io-channel-cells = <1>;
83
84            reg = <0x10070000 0x30>;
85
86            clocks = <&cgu JZ4740_CLK_ADC>;
87            clock-names = "adc";
88
89            interrupt-parent = <&intc>;
90            interrupts = <18>;
91    };
92