xref: /linux/Documentation/devicetree/bindings/iio/adc/atmel,sama5d2-adc.yaml (revision 196db6bb44738b76d7401c33aadadcea307894c2) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/iio/adc/atmel,sama5d2-adc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: AT91 SAMA5D2 Analog to Digital Converter (ADC)
8
9maintainers:
10  - Eugen Hristev <eugen.hristev@microchip.com>
11
12properties:
13  compatible:
14    enum:
15      - atmel,sama5d2-adc
16      - microchip,sam9x60-adc
17      - microchip,sama7g5-adc
18
19  reg:
20    maxItems: 1
21
22  interrupts:
23    maxItems: 1
24
25  clocks:
26    maxItems: 1
27
28  clock-names:
29    const: adc_clk
30
31  vref-supply: true
32  vddana-supply: true
33
34  atmel,min-sample-rate-hz:
35    description: Minimum sampling rate, it depends on SoC.
36
37  atmel,max-sample-rate-hz:
38    description: Maximum sampling rate, it depends on SoC.
39
40  atmel,startup-time-ms:
41    description: Startup time expressed in ms, it depends on SoC.
42
43  atmel,trigger-edge-type:
44    $ref: /schemas/types.yaml#/definitions/uint32
45    description:
46      One of possible edge types for the ADTRG hardware trigger pin.
47      When the specific edge type is detected, the conversion will
48      start. Should be one of IRQ_TYPE_EDGE_RISING, IRQ_TYPE_EDGE_FALLING
49      or IRQ_TYPE_EDGE_BOTH.
50    enum: [1, 2, 3]
51
52  dmas:
53    maxItems: 1
54
55  dma-names:
56    const: rx
57
58  "#io-channel-cells":
59    const: 1
60
61additionalProperties: false
62
63required:
64  - compatible
65  - reg
66  - interrupts
67  - clocks
68  - clock-names
69  - vref-supply
70  - vddana-supply
71  - atmel,min-sample-rate-hz
72  - atmel,max-sample-rate-hz
73  - atmel,startup-time-ms
74
75examples:
76  - |
77    #include <dt-bindings/dma/at91.h>
78    #include <dt-bindings/interrupt-controller/irq.h>
79    soc {
80        #address-cells = <1>;
81        #size-cells = <1>;
82
83        adc@fc030000 {
84            compatible = "atmel,sama5d2-adc";
85            reg = <0xfc030000 0x100>;
86            interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>;
87            clocks = <&adc_clk>;
88            clock-names = "adc_clk";
89            atmel,min-sample-rate-hz = <200000>;
90            atmel,max-sample-rate-hz = <20000000>;
91            atmel,startup-time-ms = <4>;
92            vddana-supply = <&vdd_3v3_lp_reg>;
93            vref-supply = <&vdd_3v3_lp_reg>;
94            atmel,trigger-edge-type = <IRQ_TYPE_EDGE_BOTH>;
95            dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>;
96            dma-names = "rx";
97            #io-channel-cells = <1>;
98        };
99    };
100...
101