1*96553a44SAlexandru Ardelean# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*96553a44SAlexandru Ardelean%YAML 1.2 3*96553a44SAlexandru Ardelean--- 4*96553a44SAlexandru Ardelean$id: http://devicetree.org/schemas/iio/adc/adi,axi-adc.yaml# 5*96553a44SAlexandru Ardelean$schema: http://devicetree.org/meta-schemas/core.yaml# 6*96553a44SAlexandru Ardelean 7*96553a44SAlexandru Ardeleantitle: Analog Devices AXI ADC IP core 8*96553a44SAlexandru Ardelean 9*96553a44SAlexandru Ardeleanmaintainers: 10*96553a44SAlexandru Ardelean - Michael Hennerich <michael.hennerich@analog.com> 11*96553a44SAlexandru Ardelean - Alexandru Ardelean <alexandru.ardelean@analog.com> 12*96553a44SAlexandru Ardelean 13*96553a44SAlexandru Ardeleandescription: | 14*96553a44SAlexandru Ardelean Analog Devices Generic AXI ADC IP core for interfacing an ADC device 15*96553a44SAlexandru Ardelean with a high speed serial (JESD204B/C) or source synchronous parallel 16*96553a44SAlexandru Ardelean interface (LVDS/CMOS). 17*96553a44SAlexandru Ardelean Usually, some other interface type (i.e SPI) is used as a control 18*96553a44SAlexandru Ardelean interface for the actual ADC, while this IP core will interface 19*96553a44SAlexandru Ardelean to the data-lines of the ADC and handle the streaming of data into 20*96553a44SAlexandru Ardelean memory via DMA. 21*96553a44SAlexandru Ardelean 22*96553a44SAlexandru Ardelean https://wiki.analog.com/resources/fpga/docs/axi_adc_ip 23*96553a44SAlexandru Ardelean 24*96553a44SAlexandru Ardeleanproperties: 25*96553a44SAlexandru Ardelean compatible: 26*96553a44SAlexandru Ardelean enum: 27*96553a44SAlexandru Ardelean - adi,axi-adc-10.0.a 28*96553a44SAlexandru Ardelean 29*96553a44SAlexandru Ardelean reg: 30*96553a44SAlexandru Ardelean maxItems: 1 31*96553a44SAlexandru Ardelean 32*96553a44SAlexandru Ardelean dmas: 33*96553a44SAlexandru Ardelean maxItems: 1 34*96553a44SAlexandru Ardelean 35*96553a44SAlexandru Ardelean dma-names: 36*96553a44SAlexandru Ardelean items: 37*96553a44SAlexandru Ardelean - const: rx 38*96553a44SAlexandru Ardelean 39*96553a44SAlexandru Ardelean adi,adc-dev: 40*96553a44SAlexandru Ardelean $ref: /schemas/types.yaml#/definitions/phandle 41*96553a44SAlexandru Ardelean description: 42*96553a44SAlexandru Ardelean A reference to a the actual ADC to which this FPGA ADC interfaces to. 43*96553a44SAlexandru Ardelean 44*96553a44SAlexandru Ardeleanrequired: 45*96553a44SAlexandru Ardelean - compatible 46*96553a44SAlexandru Ardelean - dmas 47*96553a44SAlexandru Ardelean - reg 48*96553a44SAlexandru Ardelean - adi,adc-dev 49*96553a44SAlexandru Ardelean 50*96553a44SAlexandru ArdeleanadditionalProperties: false 51*96553a44SAlexandru Ardelean 52*96553a44SAlexandru Ardeleanexamples: 53*96553a44SAlexandru Ardelean - | 54*96553a44SAlexandru Ardelean axi-adc@44a00000 { 55*96553a44SAlexandru Ardelean compatible = "adi,axi-adc-10.0.a"; 56*96553a44SAlexandru Ardelean reg = <0x44a00000 0x10000>; 57*96553a44SAlexandru Ardelean dmas = <&rx_dma 0>; 58*96553a44SAlexandru Ardelean dma-names = "rx"; 59*96553a44SAlexandru Ardelean 60*96553a44SAlexandru Ardelean adi,adc-dev = <&spi_adc>; 61*96553a44SAlexandru Ardelean }; 62*96553a44SAlexandru Ardelean... 63