xref: /linux/Documentation/devicetree/bindings/i3c/adi,i3c-master.yaml (revision db4a3f0fbedb0398f77b9047e8b8bb2b49f355bb) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/i3c/adi,i3c-master.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Analog Devices I3C Controller
8
9description:
10  FPGA-based I3C controller designed to interface with I3C and I2C peripherals,
11  implementing a subset of the I3C-basic specification. The IP core is tested
12  on arm, microblaze, and arm64 architectures.
13
14  https://analogdevicesinc.github.io/hdl/library/i3c_controller
15
16maintainers:
17  - Jorge Marques <jorge.marques@analog.com>
18
19properties:
20  compatible:
21    const: adi,i3c-master-v1
22
23  reg:
24    maxItems: 1
25
26  clocks:
27    minItems: 1
28    items:
29      - description: The AXI interconnect clock, drives the register map.
30      - description:
31          The secondary clock, drives the internal logic asynchronously to the
32          register map. The presence of this entry states that the IP Core was
33          synthesized with a second clock input, and the absence of this entry
34          indicates a topology where a single clock input drives all the
35          internal logic.
36
37  clock-names:
38    minItems: 1
39    items:
40      - const: axi
41      - const: i3c
42
43  interrupts:
44    maxItems: 1
45
46required:
47  - compatible
48  - reg
49  - clocks
50  - clock-names
51  - interrupts
52
53allOf:
54  - $ref: i3c.yaml#
55
56unevaluatedProperties: false
57
58examples:
59  - |
60    #include <dt-bindings/interrupt-controller/irq.h>
61
62    i3c@44a00000 {
63        compatible = "adi,i3c-master-v1";
64        reg = <0x44a00000 0x1000>;
65        interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
66        clocks = <&clkc 15>, <&clkc 15>;
67        clock-names = "axi", "i3c";
68        #address-cells = <3>;
69        #size-cells = <0>;
70
71        /* I3C and I2C devices */
72    };
73