xref: /linux/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml (revision d8d2b1f81530988abe2e2bfaceec1c5d30b9a0b4) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/i2c/qcom,i2c-geni-qcom.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Geni based QUP I2C Controller
8
9maintainers:
10  - Andy Gross <agross@kernel.org>
11  - Bjorn Andersson <bjorn.andersson@linaro.org>
12
13properties:
14  compatible:
15    enum:
16      - qcom,geni-i2c
17      - qcom,geni-i2c-master-hub
18
19  clocks:
20    minItems: 1
21    maxItems: 2
22
23  clock-names:
24    minItems: 1
25    maxItems: 2
26
27  clock-frequency:
28    default: 100000
29
30  dmas:
31    maxItems: 2
32
33  dma-names:
34    items:
35      - const: tx
36      - const: rx
37
38  interconnects:
39    minItems: 2
40    maxItems: 3
41
42  interconnect-names:
43    minItems: 2
44    maxItems: 3
45
46  interrupts:
47    maxItems: 1
48
49  operating-points-v2: true
50
51  pinctrl-0: true
52  pinctrl-1: true
53
54  pinctrl-names:
55    minItems: 1
56    items:
57      - const: default
58      - const: sleep
59
60  power-domains:
61    maxItems: 1
62
63  reg:
64    maxItems: 1
65
66  required-opps:
67    maxItems: 1
68
69required:
70  - compatible
71  - interrupts
72  - clocks
73  - clock-names
74  - reg
75
76allOf:
77  - $ref: /schemas/i2c/i2c-controller.yaml#
78  - $ref: /schemas/soc/qcom/qcom,se-common-props.yaml#
79  - if:
80      properties:
81        compatible:
82          contains:
83            const: qcom,geni-i2c-master-hub
84    then:
85      properties:
86        clocks:
87          minItems: 2
88
89        clock-names:
90          items:
91            - const: se
92            - const: core
93
94        dmas: false
95        dma-names: false
96
97        interconnects:
98          maxItems: 2
99
100        interconnect-names:
101          items:
102            - const: qup-core
103            - const: qup-config
104    else:
105      properties:
106        clocks:
107          maxItems: 1
108
109        clock-names:
110          const: se
111
112        interconnects:
113          minItems: 3
114
115        interconnect-names:
116          items:
117            - const: qup-core
118            - const: qup-config
119            - const: qup-memory
120
121unevaluatedProperties: false
122
123examples:
124  - |
125    #include <dt-bindings/interrupt-controller/arm-gic.h>
126    #include <dt-bindings/clock/qcom,gcc-sc7180.h>
127    #include <dt-bindings/interconnect/qcom,sc7180.h>
128    #include <dt-bindings/power/qcom-rpmpd.h>
129
130    i2c@88000 {
131        compatible = "qcom,geni-i2c";
132        reg = <0x00880000 0x4000>;
133        clock-names = "se";
134        clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
135        pinctrl-names = "default";
136        pinctrl-0 = <&qup_i2c0_default>;
137        interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
138        #address-cells = <1>;
139        #size-cells = <0>;
140        interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
141                        <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
142                        <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
143        interconnect-names = "qup-core", "qup-config", "qup-memory";
144        power-domains = <&rpmhpd SC7180_CX>;
145        required-opps = <&rpmhpd_opp_low_svs>;
146    };
147...
148