xref: /linux/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml (revision 0d8eae7b124e2ddaee00f186fe922450faad0ed7) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: "http://devicetree.org/schemas/i2c/qcom,i2c-geni-qcom.yaml#"
5$schema: "http://devicetree.org/meta-schemas/core.yaml#"
6
7title: Qualcomm Geni based QUP I2C Controller
8
9maintainers:
10  - Andy Gross <agross@kernel.org>
11  - Bjorn Andersson <bjorn.andersson@linaro.org>
12
13properties:
14  compatible:
15    enum:
16      - qcom,geni-i2c
17      - qcom,geni-i2c-master-hub
18
19  clocks:
20    minItems: 1
21    maxItems: 2
22
23  clock-names:
24    minItems: 1
25    maxItems: 2
26
27  clock-frequency:
28    default: 100000
29
30  dmas:
31    maxItems: 2
32
33  dma-names:
34    items:
35      - const: tx
36      - const: rx
37
38  interconnects:
39    minItems: 2
40    maxItems: 3
41
42  interconnect-names:
43    minItems: 2
44    maxItems: 3
45
46  interrupts:
47    maxItems: 1
48
49  pinctrl-0: true
50  pinctrl-1: true
51
52  pinctrl-names:
53    minItems: 1
54    items:
55      - const: default
56      - const: sleep
57
58  power-domains:
59    maxItems: 1
60
61  reg:
62    maxItems: 1
63
64  required-opps:
65    maxItems: 1
66
67required:
68  - compatible
69  - interrupts
70  - clocks
71  - clock-names
72  - reg
73
74allOf:
75  - $ref: /schemas/i2c/i2c-controller.yaml#
76  - if:
77      properties:
78        compatible:
79          contains:
80            const: qcom,geni-i2c-master-hub
81    then:
82      properties:
83        clocks:
84          minItems: 2
85
86        clock-names:
87          items:
88            - const: se
89            - const: core
90
91        dmas: false
92        dma-names: false
93
94        interconnects:
95          maxItems: 2
96
97        interconnect-names:
98          items:
99            - const: qup-core
100            - const: qup-config
101    else:
102      properties:
103        clocks:
104          maxItems: 1
105
106        clock-names:
107          const: se
108
109        interconnects:
110          minItems: 3
111
112        interconnect-names:
113          items:
114            - const: qup-core
115            - const: qup-config
116            - const: qup-memory
117
118unevaluatedProperties: false
119
120examples:
121  - |
122    #include <dt-bindings/interrupt-controller/arm-gic.h>
123    #include <dt-bindings/clock/qcom,gcc-sc7180.h>
124    #include <dt-bindings/interconnect/qcom,sc7180.h>
125    #include <dt-bindings/power/qcom-rpmpd.h>
126
127    i2c@88000 {
128        compatible = "qcom,geni-i2c";
129        reg = <0x00880000 0x4000>;
130        clock-names = "se";
131        clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
132        pinctrl-names = "default";
133        pinctrl-0 = <&qup_i2c0_default>;
134        interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
135        #address-cells = <1>;
136        #size-cells = <0>;
137        interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
138                        <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
139                        <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
140        interconnect-names = "qup-core", "qup-config", "qup-memory";
141        power-domains = <&rpmhpd SC7180_CX>;
142        required-opps = <&rpmhpd_opp_low_svs>;
143    };
144...
145