xref: /linux/Documentation/devicetree/bindings/i2c/microchip,corei2c.yaml (revision 7f71507851fc7764b36a3221839607d3a45c2025) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/i2c/microchip,corei2c.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Microchip MPFS I2C Controller
8
9maintainers:
10  - Daire McNamara <daire.mcnamara@microchip.com>
11
12allOf:
13  - $ref: /schemas/i2c/i2c-controller.yaml#
14
15properties:
16  compatible:
17    oneOf:
18      - items:
19          - enum:
20              - microchip,pic64gx-i2c
21              - microchip,mpfs-i2c # Microchip PolarFire SoC compatible SoCs
22          - const: microchip,corei2c-rtl-v7 # Microchip Fabric based i2c IP core
23      - const: microchip,corei2c-rtl-v7 # Microchip Fabric based i2c IP core
24
25  reg:
26    maxItems: 1
27
28  interrupts:
29    maxItems: 1
30
31  clocks:
32    maxItems: 1
33
34  clock-frequency:
35    description: |
36      Desired I2C bus clock frequency in Hz. As only Standard and Fast
37      modes are supported, possible values are 100000 and 400000.
38    enum: [100000, 400000]
39
40required:
41  - compatible
42  - reg
43  - interrupts
44  - clocks
45
46unevaluatedProperties: false
47
48examples:
49  - |
50    i2c@2010a000 {
51      compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7";
52      reg = <0x2010a000 0x1000>;
53      clocks = <&clkcfg 15>;
54      interrupt-parent = <&plic>;
55      interrupts = <58>;
56      clock-frequency = <100000>;
57    };
58...
59