xref: /linux/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.yaml (revision a1ff5a7d78a036d6c2178ee5acd6ba4946243800) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/i2c/i2c-imx-lpi2c.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Freescale Low Power Inter IC (LPI2C) for i.MX
8
9maintainers:
10  - Shawn Guo <shawnguo@kernel.org>
11  - Sascha Hauer <s.hauer@pengutronix.de>
12  - Fabio Estevam <festevam@gmail.com>
13
14allOf:
15  - $ref: /schemas/i2c/i2c-controller.yaml#
16
17properties:
18  compatible:
19    oneOf:
20      - enum:
21          - fsl,imx7ulp-lpi2c
22      - items:
23          - enum:
24              - fsl,imx8qxp-lpi2c
25              - fsl,imx8dxl-lpi2c
26              - fsl,imx8qm-lpi2c
27              - fsl,imx8ulp-lpi2c
28              - fsl,imx93-lpi2c
29              - fsl,imx95-lpi2c
30          - const: fsl,imx7ulp-lpi2c
31
32  reg:
33    maxItems: 1
34
35  interrupts:
36    maxItems: 1
37
38  assigned-clock-parents: true
39  assigned-clock-rates: true
40  assigned-clocks: true
41  clock-frequency: true
42
43  clock-names:
44    items:
45      - const: per
46      - const: ipg
47
48  clocks:
49    maxItems: 2
50
51  dmas:
52    items:
53      - description: DMA controller phandle and request line for TX
54      - description: DMA controller phandle and request line for RX
55
56  dma-names:
57    items:
58      - const: tx
59      - const: rx
60
61  power-domains:
62    maxItems: 1
63
64required:
65  - compatible
66  - reg
67  - interrupts
68  - clocks
69
70unevaluatedProperties: false
71
72examples:
73  - |
74    #include <dt-bindings/clock/imx7ulp-clock.h>
75    #include <dt-bindings/interrupt-controller/arm-gic.h>
76
77    i2c@40a50000 {
78        compatible = "fsl,imx7ulp-lpi2c";
79        reg = <0x40A50000 0x10000>;
80        interrupt-parent = <&intc>;
81        interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
82        clocks = <&clks IMX7ULP_CLK_LPI2C7>,
83                 <&clks IMX7ULP_CLK_NIC1_BUS_DIV>;
84    };
85