1*15ef2775SWei YanI2C for Hisilicon hix5hd2 chipset platform 2*15ef2775SWei Yan 3*15ef2775SWei YanRequired properties: 4*15ef2775SWei Yan- compatible: Must be "hisilicon,hix5hd2-i2c" 5*15ef2775SWei Yan- reg: physical base address of the controller and length of memory mapped 6*15ef2775SWei Yan region. 7*15ef2775SWei Yan- interrupts: interrupt number to the cpu. 8*15ef2775SWei Yan- #address-cells = <1>; 9*15ef2775SWei Yan- #size-cells = <0>; 10*15ef2775SWei Yan- clocks: phandles to input clocks. 11*15ef2775SWei Yan 12*15ef2775SWei YanOptional properties: 13*15ef2775SWei Yan- clock-frequency: Desired I2C bus frequency in Hz, otherwise defaults to 100000 14*15ef2775SWei Yan- Child nodes conforming to i2c bus binding 15*15ef2775SWei Yan 16*15ef2775SWei YanExamples: 17*15ef2775SWei YanI2C0@f8b10000 { 18*15ef2775SWei Yan compatible = "hisilicon,hix5hd2-i2c"; 19*15ef2775SWei Yan reg = <0xf8b10000 0x1000>; 20*15ef2775SWei Yan interrupts = <0 38 4>; 21*15ef2775SWei Yan clocks = <&clock HIX5HD2_I2C0_RST>; 22*15ef2775SWei Yan #address-cells = <1>; 23*15ef2775SWei Yan #size-cells = <0>; 24*15ef2775SWei Yan} 25