xref: /linux/Documentation/devicetree/bindings/i2c/hpe,gxp-i2c.yaml (revision 24168c5e6dfbdd5b414f048f47f75d64533296ca) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/i2c/hpe,gxp-i2c.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: HPE GXP SoC I2C Controller
8
9maintainers:
10  - Nick Hawkins <nick.hawkins@hpe.com>
11
12allOf:
13  - $ref: /schemas/i2c/i2c-controller.yaml#
14
15properties:
16  compatible:
17    const: hpe,gxp-i2c
18
19  reg:
20    maxItems: 1
21
22  interrupts:
23    maxItems: 1
24
25  clock-frequency:
26    default: 100000
27
28  hpe,sysreg:
29    $ref: /schemas/types.yaml#/definitions/phandle
30    description:
31      Phandle to the global status and enable interrupt registers shared
32      between each I2C engine controller instance. It enables the I2C
33      engine controller to act as both a master or slave by being able to
34      arm and respond to interrupts from its engine. Each bit in the
35      registers represent the respective bit position.
36
37required:
38  - compatible
39  - reg
40  - interrupts
41
42unevaluatedProperties: false
43
44examples:
45  - |
46    i2c@2600 {
47        compatible = "hpe,gxp-i2c";
48        reg = <0x2500 0x70>;
49        interrupts = <9>;
50        #address-cells = <1>;
51        #size-cells = <0>;
52        hpe,sysreg = <&sysreg_system_controller>;
53        clock-frequency = <10000>;
54
55        eeprom@50 {
56            compatible = "atmel,24c128";
57            reg = <0x50>;
58        };
59    };
60