xref: /linux/Documentation/devicetree/bindings/gpu/nvidia,gk20a.yaml (revision b615879dbfea6cf1236acbc3f2fb25ae84e07071) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/gpu/nvidia,gk20a.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra Graphics Processing Units
8
9maintainers:
10  - Alexandre Courbot <acourbot@nvidia.com>
11  - Jon Hunter <jonathanh@nvidia.com>
12  - Thierry Reding <treding@nvidia.com>
13
14properties:
15  compatible:
16    enum:
17      - nvidia,gk20a
18      - nvidia,gm20b
19      - nvidia,gp10b
20      - nvidia,gv11b
21
22  reg:
23    items:
24      - description: Bar0 register window
25      - description: Bar1 register window
26
27  interrupts:
28    items:
29      - description: Stall interrupt
30      - description: Nonstall interrupt
31
32  interrupt-names:
33    items:
34      - const: stall
35      - const: nonstall
36
37  vdd-supply:
38    description:
39      Regulator for GPU supply voltage
40
41  clocks:
42    minItems: 2
43    items:
44      - description: GPU clock
45      - description: Power clock
46      - description: Reference or fuse clock
47
48  clock-names:
49    minItems: 2
50    items:
51      - const: gpu
52      - const: pwr
53      - enum: [ ref, fuse ]
54
55  resets:
56    maxItems: 1
57
58  reset-names:
59    items:
60      - const: gpu
61
62  power-domains:
63    maxItems: 1
64
65  interconnects:
66    minItems: 4
67    maxItems: 12
68
69  interconnect-names:
70    minItems: 4
71    maxItems: 12
72
73  iommus:
74    maxItems: 1
75
76  dma-coherent: true
77
78required:
79  - compatible
80  - reg
81  - interrupts
82  - interrupt-names
83  - clocks
84  - clock-names
85  - resets
86  - reset-names
87
88allOf:
89  - if:
90      properties:
91        compatible:
92          contains:
93            enum:
94              - nvidia,gp10b
95              - nvidia,gv11b
96    then:
97      required:
98        - power-domains
99    else:
100      properties:
101        interconnects: false
102        interconnect-names: false
103
104      required:
105        - vdd-supply
106  - if:
107      properties:
108        compatible:
109          contains:
110            enum:
111              - nvidia,gp10b
112    then:
113      properties:
114        interconnects:
115          maxItems: 4
116
117        interconnect-names:
118          items:
119            - const: dma-mem
120            - const: write-0
121            - const: read-1
122            - const: write-1
123  - if:
124      properties:
125        compatible:
126          contains:
127            enum:
128              - nvidia,gv11b
129    then:
130      properties:
131        interconnects:
132          minItems: 12
133
134        interconnect-names:
135          items:
136            - const: dma-mem
137            - const: read-0-hp
138            - const: write-0
139            - const: read-1
140            - const: read-1-hp
141            - const: write-1
142            - const: read-2
143            - const: read-2-hp
144            - const: write-2
145            - const: read-3
146            - const: read-3-hp
147            - const: write-3
148
149additionalProperties: false
150
151examples:
152  - |
153    #include <dt-bindings/interrupt-controller/arm-gic.h>
154    #include <dt-bindings/clock/tegra124-car-common.h>
155    #include <dt-bindings/memory/tegra124-mc.h>
156
157    gpu@57000000 {
158        compatible = "nvidia,gk20a";
159        reg = <0x57000000 0x01000000>,
160              <0x58000000 0x01000000>;
161        interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
162                     <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
163        interrupt-names = "stall", "nonstall";
164        vdd-supply = <&vdd_gpu>;
165        clocks = <&tegra_car TEGRA124_CLK_GPU>,
166                 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
167        clock-names = "gpu", "pwr";
168        resets = <&tegra_car 184>;
169        reset-names = "gpu";
170        iommus = <&mc TEGRA_SWGROUP_GPU>;
171    };
172