1NVIDIA Tegra Graphics Processing Units 2 3Required properties: 4- compatible: "nvidia,<gpu>" 5 Currently recognized values: 6 - nvidia,gk20a 7 - nvidia,gm20b 8 - nvidia,gp10b 9- reg: Physical base address and length of the controller's registers. 10 Must contain two entries: 11 - first entry for bar0 12 - second entry for bar1 13- interrupts: Must contain an entry for each entry in interrupt-names. 14 See ../interrupt-controller/interrupts.txt for details. 15- interrupt-names: Must include the following entries: 16 - stall 17 - nonstall 18- vdd-supply: regulator for supply voltage. Only required for GPUs not using 19 power domains. 20- clocks: Must contain an entry for each entry in clock-names. 21 See ../clocks/clock-bindings.txt for details. 22- clock-names: Must include the following entries: 23 - gpu 24 - pwr 25If the compatible string is "nvidia,gm20b", then the following clock 26is also required: 27 - ref 28- resets: Must contain an entry for each entry in reset-names. 29 See ../reset/reset.txt for details. 30- reset-names: Must include the following entries: 31 - gpu 32- power-domains: GPUs that make use of power domains can define this property 33 instead of vdd-supply. Currently "nvidia,gp10b" makes use of this. 34 35Optional properties: 36- iommus: A reference to the IOMMU. See ../iommu/iommu.txt for details. 37 38Example for GK20A: 39 40 gpu@57000000 { 41 compatible = "nvidia,gk20a"; 42 reg = <0x0 0x57000000 0x0 0x01000000>, 43 <0x0 0x58000000 0x0 0x01000000>; 44 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 45 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 46 interrupt-names = "stall", "nonstall"; 47 vdd-supply = <&vdd_gpu>; 48 clocks = <&tegra_car TEGRA124_CLK_GPU>, 49 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; 50 clock-names = "gpu", "pwr"; 51 resets = <&tegra_car 184>; 52 reset-names = "gpu"; 53 iommus = <&mc TEGRA_SWGROUP_GPU>; 54 }; 55 56Example for GM20B: 57 58 gpu@57000000 { 59 compatible = "nvidia,gm20b"; 60 reg = <0x0 0x57000000 0x0 0x01000000>, 61 <0x0 0x58000000 0x0 0x01000000>; 62 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 64 interrupt-names = "stall", "nonstall"; 65 clocks = <&tegra_car TEGRA210_CLK_GPU>, 66 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>, 67 <&tegra_car TEGRA210_CLK_PLL_G_REF>; 68 clock-names = "gpu", "pwr", "ref"; 69 resets = <&tegra_car 184>; 70 reset-names = "gpu"; 71 iommus = <&mc TEGRA_SWGROUP_GPU>; 72 }; 73 74Example for GP10B: 75 76 gpu@17000000 { 77 compatible = "nvidia,gp10b"; 78 reg = <0x0 0x17000000 0x0 0x1000000>, 79 <0x0 0x18000000 0x0 0x1000000>; 80 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH 81 GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 82 interrupt-names = "stall", "nonstall"; 83 clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 84 <&bpmp TEGRA186_CLK_GPU>; 85 clock-names = "gpu", "pwr"; 86 resets = <&bpmp TEGRA186_RESET_GPU>; 87 reset-names = "gpu"; 88 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 89 iommus = <&smmu TEGRA186_SID_GPU>; 90 }; 91