xref: /linux/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml (revision be1ca3ee8f97067fee87fda73ea5959d5ab75bbf) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/gpu/arm,mali-valhall-csf.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM Mali Valhall GPU
8
9maintainers:
10  - Liviu Dudau <liviu.dudau@arm.com>
11  - Boris Brezillon <boris.brezillon@collabora.com>
12
13properties:
14  $nodename:
15    pattern: '^gpu@[a-f0-9]+$'
16
17  compatible:
18    oneOf:
19      - items:
20          - enum:
21              - mediatek,mt8196-mali
22              - nxp,imx95-mali            # G310
23              - rockchip,rk3588-mali
24          - const: arm,mali-valhall-csf   # Mali Valhall GPU model/revision is fully discoverable
25
26  reg:
27    maxItems: 1
28
29  interrupts:
30    items:
31      - description: Job interrupt
32      - description: MMU interrupt
33      - description: GPU interrupt
34
35  interrupt-names:
36    items:
37      - const: job
38      - const: mmu
39      - const: gpu
40
41  clocks:
42    minItems: 1
43    maxItems: 3
44
45  clock-names:
46    minItems: 1
47    items:
48      - const: core
49      - enum:
50          - coregroup
51          - stacks
52      - const: stacks
53
54  nvmem-cells:
55    items:
56      - description: bitmask of functional shader cores
57
58  nvmem-cell-names:
59    items:
60      - const: shader-present
61
62  mali-supply: true
63
64  operating-points-v2: true
65  opp-table:
66    type: object
67
68  power-domains:
69    minItems: 1
70    maxItems: 5
71
72  power-domain-names:
73    minItems: 1
74    maxItems: 5
75
76  sram-supply: true
77
78  "#cooling-cells":
79    const: 2
80
81  dynamic-power-coefficient:
82    $ref: /schemas/types.yaml#/definitions/uint32
83    description:
84      A u32 value that represents the running time dynamic
85      power coefficient in units of uW/MHz/V^2. The
86      coefficient can either be calculated from power
87      measurements or derived by analysis.
88
89      The dynamic power consumption of the GPU is
90      proportional to the square of the Voltage (V) and
91      the clock frequency (f). The coefficient is used to
92      calculate the dynamic power as below -
93
94      Pdyn = dynamic-power-coefficient * V^2 * f
95
96      where voltage is in V, frequency is in MHz.
97
98  dma-coherent: true
99
100required:
101  - compatible
102  - reg
103  - interrupts
104  - interrupt-names
105  - clocks
106
107additionalProperties: false
108
109allOf:
110  - if:
111      properties:
112        compatible:
113          contains:
114            const: rockchip,rk3588-mali
115    then:
116      properties:
117        clocks:
118          minItems: 3
119        nvmem-cells: false
120        nvmem-cell-names: false
121        power-domains:
122          maxItems: 1
123        power-domain-names: false
124      required:
125        - mali-supply
126  - if:
127      properties:
128        compatible:
129          contains:
130            const: mediatek,mt8196-mali
131    then:
132      properties:
133        mali-supply: false
134        sram-supply: false
135        operating-points-v2: false
136        power-domains:
137          maxItems: 1
138        power-domain-names: false
139        clocks:
140          maxItems: 2
141        clock-names:
142          items:
143            - const: core
144            - const: stacks
145      required:
146        - nvmem-cells
147        - nvmem-cell-names
148        - power-domains
149
150examples:
151  - |
152    #include <dt-bindings/clock/rockchip,rk3588-cru.h>
153    #include <dt-bindings/interrupt-controller/irq.h>
154    #include <dt-bindings/interrupt-controller/arm-gic.h>
155    #include <dt-bindings/power/rk3588-power.h>
156
157    gpu: gpu@fb000000 {
158        compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf";
159        reg = <0xfb000000 0x200000>;
160        interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>,
161                     <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>,
162                     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>;
163        interrupt-names = "job", "mmu", "gpu";
164        clock-names = "core", "coregroup", "stacks";
165        clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>,
166                 <&cru CLK_GPU_STACKS>;
167        power-domains = <&power RK3588_PD_GPU>;
168        operating-points-v2 = <&gpu_opp_table>;
169        mali-supply = <&vdd_gpu_s0>;
170        sram-supply = <&vdd_gpu_mem_s0>;
171
172        gpu_opp_table: opp-table {
173            compatible = "operating-points-v2";
174            opp-300000000 {
175                opp-hz = /bits/ 64 <300000000>;
176                opp-microvolt = <675000 675000 850000>;
177            };
178            opp-400000000 {
179                opp-hz = /bits/ 64 <400000000>;
180                opp-microvolt = <675000 675000 850000>;
181            };
182        };
183    };
184  - |
185    gpu@48000000 {
186        compatible = "mediatek,mt8196-mali", "arm,mali-valhall-csf";
187        reg = <0x48000000 0x480000>;
188        clocks = <&gpufreq 0>, <&gpufreq 1>;
189        clock-names = "core", "stacks";
190        interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH 0>,
191                     <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH 0>,
192                     <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH 0>;
193        interrupt-names = "job", "mmu", "gpu";
194        nvmem-cells = <&shader_present>;
195        nvmem-cell-names = "shader-present";
196        power-domains = <&gpufreq>;
197    };
198
199...
200