1# SPDX-License-Identifier: GPL-2.0-only 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/gpu/arm,mali-utgard.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: ARM Mali Utgard GPU 8 9maintainers: 10 - Rob Herring <robh@kernel.org> 11 - Maxime Ripard <mripard@kernel.org> 12 - Heiko Stuebner <heiko@sntech.de> 13 14properties: 15 $nodename: 16 pattern: '^gpu@[a-f0-9]+$' 17 compatible: 18 oneOf: 19 - items: 20 - const: allwinner,sun8i-a23-mali 21 - const: allwinner,sun7i-a20-mali 22 - const: arm,mali-400 23 - items: 24 - enum: 25 - allwinner,sun4i-a10-mali 26 - allwinner,sun7i-a20-mali 27 - allwinner,sun8i-h3-mali 28 - allwinner,sun8i-r40-mali 29 - allwinner,sun50i-a64-mali 30 - rockchip,rk3036-mali 31 - rockchip,rk3066-mali 32 - rockchip,rk3128-mali 33 - rockchip,rk3188-mali 34 - rockchip,rk3228-mali 35 - samsung,exynos4210-mali 36 - st,stih410-mali 37 - stericsson,db8500-mali 38 - xlnx,zynqmp-mali 39 - const: arm,mali-400 40 - items: 41 - enum: 42 - allwinner,sun50i-h5-mali 43 - amlogic,meson8-mali 44 - amlogic,meson8b-mali 45 - amlogic,meson-gxbb-mali 46 - amlogic,meson-gxl-mali 47 - hisilicon,hi6220-mali 48 - mediatek,mt7623-mali 49 - rockchip,rk3328-mali 50 - rockchip,rk3528-mali 51 - const: arm,mali-450 52 53 # "arm,mali-300" 54 55 reg: 56 maxItems: 1 57 58 interrupts: 59 minItems: 4 60 maxItems: 20 61 62 interrupt-names: 63 allOf: 64 - additionalItems: true 65 minItems: 4 66 maxItems: 20 67 items: 68 # At least enforce the first 2 interrupts 69 - const: gp 70 - const: gpmmu 71 - items: 72 # Not ideal as any order and combination are allowed 73 enum: 74 - gp # Geometry Processor interrupt 75 - gpmmu # Geometry Processor MMU interrupt 76 - pp # Pixel Processor broadcast interrupt (mali-450 only) 77 - pp0 # Pixel Processor X interrupt (X from 0 to 7) 78 - ppmmu0 # Pixel Processor X MMU interrupt (X from 0 to 7) 79 - pp1 80 - ppmmu1 81 - pp2 82 - ppmmu2 83 - pp3 84 - ppmmu3 85 - pp4 86 - ppmmu4 87 - pp5 88 - ppmmu5 89 - pp6 90 - ppmmu6 91 - pp7 92 - ppmmu7 93 - pmu # Power Management Unit interrupt (optional) 94 - combined # stericsson,db8500-mali only 95 96 clocks: 97 maxItems: 2 98 99 clock-names: 100 items: 101 - const: bus 102 - const: core 103 104 memory-region: true 105 106 mali-supply: true 107 108 opp-table: 109 type: object 110 111 power-domains: 112 maxItems: 1 113 114 resets: 115 maxItems: 1 116 117 operating-points-v2: true 118 119 "#cooling-cells": 120 const: 2 121 122required: 123 - compatible 124 - reg 125 - interrupts 126 - interrupt-names 127 - clocks 128 - clock-names 129 130additionalProperties: false 131 132allOf: 133 - if: 134 properties: 135 compatible: 136 contains: 137 enum: 138 - allwinner,sun4i-a10-mali 139 - allwinner,sun7i-a20-mali 140 - allwinner,sun8i-r40-mali 141 - allwinner,sun50i-a64-mali 142 - allwinner,sun50i-h5-mali 143 - amlogic,meson8-mali 144 - amlogic,meson8b-mali 145 - hisilicon,hi6220-mali 146 - mediatek,mt7623-mali 147 - rockchip,rk3036-mali 148 - rockchip,rk3066-mali 149 - rockchip,rk3188-mali 150 - rockchip,rk3228-mali 151 - rockchip,rk3328-mali 152 - rockchip,rk3528-mali 153 then: 154 required: 155 - resets 156 157examples: 158 - | 159 #include <dt-bindings/interrupt-controller/irq.h> 160 #include <dt-bindings/interrupt-controller/arm-gic.h> 161 162 mali: gpu@1c40000 { 163 compatible = "allwinner,sun7i-a20-mali", "arm,mali-400"; 164 reg = <0x01c40000 0x10000>; 165 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 168 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 169 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 170 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 171 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 172 interrupt-names = "gp", 173 "gpmmu", 174 "pp0", 175 "ppmmu0", 176 "pp1", 177 "ppmmu1", 178 "pmu"; 179 clocks = <&ccu 1>, <&ccu 2>; 180 clock-names = "bus", "core"; 181 resets = <&ccu 1>; 182 #cooling-cells = <2>; 183 }; 184 185... 186