1657a06dfSSerge Semin# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2657a06dfSSerge Semin%YAML 1.2 3657a06dfSSerge Semin--- 4657a06dfSSerge Semin$id: http://devicetree.org/schemas/gpio/snps,dw-apb-gpio.yaml# 5657a06dfSSerge Semin$schema: http://devicetree.org/meta-schemas/core.yaml# 6657a06dfSSerge Semin 7657a06dfSSerge Semintitle: Synopsys DesignWare APB GPIO controller 8657a06dfSSerge Semin 9657a06dfSSerge Semindescription: | 10657a06dfSSerge Semin Synopsys DesignWare GPIO controllers have a configurable number of ports, 11657a06dfSSerge Semin each of which are intended to be represented as child nodes with the generic 12657a06dfSSerge Semin GPIO-controller properties as desribed in this bindings file. 13657a06dfSSerge Semin 14657a06dfSSerge Seminmaintainers: 15657a06dfSSerge Semin - Hoan Tran <hoan@os.amperecomputing.com> 16657a06dfSSerge Semin 17657a06dfSSerge Seminproperties: 18657a06dfSSerge Semin $nodename: 19657a06dfSSerge Semin pattern: "^gpio@[0-9a-f]+$" 20657a06dfSSerge Semin 21657a06dfSSerge Semin compatible: 22657a06dfSSerge Semin const: snps,dw-apb-gpio 23657a06dfSSerge Semin 24657a06dfSSerge Semin "#address-cells": 25657a06dfSSerge Semin const: 1 26657a06dfSSerge Semin 27657a06dfSSerge Semin "#size-cells": 28657a06dfSSerge Semin const: 0 29657a06dfSSerge Semin 30657a06dfSSerge Semin reg: 31657a06dfSSerge Semin maxItems: 1 32657a06dfSSerge Semin 33657a06dfSSerge Semin clocks: 34*4f180937SSerge Semin minItems: 1 35657a06dfSSerge Semin items: 36657a06dfSSerge Semin - description: APB interface clock source 37*4f180937SSerge Semin - description: DW GPIO debounce reference clock source 38657a06dfSSerge Semin 39657a06dfSSerge Semin clock-names: 40*4f180937SSerge Semin minItems: 1 41657a06dfSSerge Semin items: 42657a06dfSSerge Semin - const: bus 43*4f180937SSerge Semin - const: db 44657a06dfSSerge Semin 45657a06dfSSerge Semin resets: 46657a06dfSSerge Semin maxItems: 1 47657a06dfSSerge Semin 48657a06dfSSerge SeminpatternProperties: 49657a06dfSSerge Semin "^gpio-(port|controller)@[0-9a-f]+$": 50657a06dfSSerge Semin type: object 51657a06dfSSerge Semin properties: 52657a06dfSSerge Semin compatible: 53657a06dfSSerge Semin const: snps,dw-apb-gpio-port 54657a06dfSSerge Semin 55657a06dfSSerge Semin reg: 56657a06dfSSerge Semin maxItems: 1 57657a06dfSSerge Semin 58657a06dfSSerge Semin gpio-controller: true 59657a06dfSSerge Semin 60657a06dfSSerge Semin '#gpio-cells': 61657a06dfSSerge Semin const: 2 62657a06dfSSerge Semin 63657a06dfSSerge Semin snps,nr-gpios: 64657a06dfSSerge Semin description: The number of GPIO pins exported by the port. 65657a06dfSSerge Semin default: 32 66657a06dfSSerge Semin allOf: 67657a06dfSSerge Semin - $ref: /schemas/types.yaml#/definitions/uint32 68657a06dfSSerge Semin - minimum: 1 69657a06dfSSerge Semin maximum: 32 70657a06dfSSerge Semin 71657a06dfSSerge Semin interrupts: 72657a06dfSSerge Semin description: | 73657a06dfSSerge Semin The interrupts to the parent controller raised when GPIOs generate 74657a06dfSSerge Semin the interrupts. If the controller provides one combined interrupt 75657a06dfSSerge Semin for all GPIOs, specify a single interrupt. If the controller provides 76657a06dfSSerge Semin one interrupt for each GPIO, provide a list of interrupts that 77657a06dfSSerge Semin correspond to each of the GPIO pins. 78657a06dfSSerge Semin minItems: 1 79657a06dfSSerge Semin maxItems: 32 80657a06dfSSerge Semin 81657a06dfSSerge Semin interrupt-controller: true 82657a06dfSSerge Semin 83657a06dfSSerge Semin '#interrupt-cells': 84657a06dfSSerge Semin const: 2 85657a06dfSSerge Semin 86657a06dfSSerge Semin required: 87657a06dfSSerge Semin - compatible 88657a06dfSSerge Semin - reg 89657a06dfSSerge Semin - gpio-controller 90657a06dfSSerge Semin - '#gpio-cells' 91657a06dfSSerge Semin 92657a06dfSSerge Semin dependencies: 93657a06dfSSerge Semin interrupt-controller: [ interrupts ] 94657a06dfSSerge Semin 95657a06dfSSerge Semin additionalProperties: false 96657a06dfSSerge Semin 97657a06dfSSerge SeminadditionalProperties: false 98657a06dfSSerge Semin 99657a06dfSSerge Seminrequired: 100657a06dfSSerge Semin - compatible 101657a06dfSSerge Semin - reg 102657a06dfSSerge Semin - "#address-cells" 103657a06dfSSerge Semin - "#size-cells" 104657a06dfSSerge Semin 105657a06dfSSerge Seminexamples: 106657a06dfSSerge Semin - | 107657a06dfSSerge Semin gpio: gpio@20000 { 108657a06dfSSerge Semin compatible = "snps,dw-apb-gpio"; 109657a06dfSSerge Semin reg = <0x20000 0x1000>; 110657a06dfSSerge Semin #address-cells = <1>; 111657a06dfSSerge Semin #size-cells = <0>; 112657a06dfSSerge Semin 113657a06dfSSerge Semin porta: gpio-port@0 { 114657a06dfSSerge Semin compatible = "snps,dw-apb-gpio-port"; 115657a06dfSSerge Semin reg = <0>; 116657a06dfSSerge Semin gpio-controller; 117657a06dfSSerge Semin #gpio-cells = <2>; 118657a06dfSSerge Semin snps,nr-gpios = <8>; 119657a06dfSSerge Semin interrupt-controller; 120657a06dfSSerge Semin #interrupt-cells = <2>; 121657a06dfSSerge Semin interrupt-parent = <&vic1>; 122657a06dfSSerge Semin interrupts = <0>; 123657a06dfSSerge Semin }; 124657a06dfSSerge Semin 125657a06dfSSerge Semin portb: gpio-port@1 { 126657a06dfSSerge Semin compatible = "snps,dw-apb-gpio-port"; 127657a06dfSSerge Semin reg = <1>; 128657a06dfSSerge Semin gpio-controller; 129657a06dfSSerge Semin #gpio-cells = <2>; 130657a06dfSSerge Semin snps,nr-gpios = <8>; 131657a06dfSSerge Semin }; 132657a06dfSSerge Semin }; 133657a06dfSSerge Semin... 134