1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/gpio/rockchip,gpio-bank.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Rockchip GPIO bank 8 9maintainers: 10 - Heiko Stuebner <heiko@sntech.de> 11 12properties: 13 compatible: 14 enum: 15 - rockchip,gpio-bank 16 - rockchip,rk3188-gpio-bank0 17 18 reg: 19 maxItems: 1 20 21 interrupts: 22 maxItems: 1 23 24 clocks: 25 minItems: 1 26 items: 27 - description: APB interface clock source 28 - description: GPIO debounce reference clock source 29 30 gpio-ranges: true 31 32 gpio-controller: true 33 34 gpio-line-names: true 35 36 "#gpio-cells": 37 const: 2 38 39 interrupt-controller: true 40 41 "#interrupt-cells": 42 const: 2 43 44 power-domains: 45 maxItems: 1 46 47patternProperties: 48 "^.+-hog(-[0-9]+)?$": 49 type: object 50 51 required: 52 - gpio-hog 53 54required: 55 - compatible 56 - reg 57 - interrupts 58 - clocks 59 - gpio-controller 60 - "#gpio-cells" 61 - interrupt-controller 62 - "#interrupt-cells" 63 64additionalProperties: false 65 66examples: 67 - | 68 #include <dt-bindings/interrupt-controller/arm-gic.h> 69 pinctrl: pinctrl { 70 #address-cells = <1>; 71 #size-cells = <1>; 72 ranges; 73 74 gpio0: gpio@2000a000 { 75 compatible = "rockchip,rk3188-gpio-bank0"; 76 reg = <0x2000a000 0x100>; 77 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 78 clocks = <&clk_gates8 9>; 79 80 gpio-controller; 81 #gpio-cells = <2>; 82 83 interrupt-controller; 84 #interrupt-cells = <2>; 85 }; 86 87 gpio1: gpio@2003c000 { 88 compatible = "rockchip,gpio-bank"; 89 reg = <0x2003c000 0x100>; 90 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 91 clocks = <&clk_gates8 10>; 92 93 gpio-controller; 94 #gpio-cells = <2>; 95 96 interrupt-controller; 97 #interrupt-cells = <2>; 98 }; 99 }; 100